Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585852
A. Dewey
The emergence of the importance of VLSI design automation and the VLSI custom/semicustom industry has spurred a wide-spread interest in hardware description languages. Starting in 1981, the VHSIC Program has acted as a catalyst to develop a standard hardware description language that could beneficially serve the government, industry, and academic communities. This panel will discuss from different viewpoints the issues associated with VLSI interoperability standards and the potential role of the VHSIC Hardware Description Language.
{"title":"The VHSIC Hardware Description Language (VHDL) Program","authors":"A. Dewey","doi":"10.1109/DAC.1984.1585852","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585852","url":null,"abstract":"The emergence of the importance of VLSI design automation and the VLSI custom/semicustom industry has spurred a wide-spread interest in hardware description languages. Starting in 1981, the VHSIC Program has acted as a catalyst to develop a standard hardware description language that could beneficially serve the government, industry, and academic communities. This panel will discuss from different viewpoints the issues associated with VLSI interoperability standards and the potential role of the VHSIC Hardware Description Language.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115484717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585851
Tsuyoshi Takahashi, Satoshi Kojima, O. Yamashiro, Kazuhiko Eguchi, H. Fukuda
A novel analytical model of MOS digital networks, which is based on a modified Thevenin equivalent, is described. The model can handle all the primary circuits inherent in MOS technology, such as transistor logics, wired-ORs, tri-state circuits, charge-share operation, and bidirectional pass transistors etc., with precise estimation of delay time. The model has been implemented in a logic/fault simulator, named HASL-GT. Performance of 4 to 10 k events/sec has been obtained on HITAC M-200H(8MIPS). Fault simulation capability has also been implemented using the concurrent method.
{"title":"An MOS Digital Network Model on a Modified Thevenin Equivalent for Logic Simulation","authors":"Tsuyoshi Takahashi, Satoshi Kojima, O. Yamashiro, Kazuhiko Eguchi, H. Fukuda","doi":"10.1109/DAC.1984.1585851","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585851","url":null,"abstract":"A novel analytical model of MOS digital networks, which is based on a modified Thevenin equivalent, is described. The model can handle all the primary circuits inherent in MOS technology, such as transistor logics, wired-ORs, tri-state circuits, charge-share operation, and bidirectional pass transistors etc., with precise estimation of delay time. The model has been implemented in a logic/fault simulator, named HASL-GT. Performance of 4 to 10 k events/sec has been obtained on HITAC M-200H(8MIPS). Fault simulation capability has also been implemented using the concurrent method.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117154931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585835
V. J. Freund
In its highly automated East Fishkill semiconductor facility, IBM has exploited the "gate array" concept to its fullest in the support of computers designed using VLSI. IBM's Engineering Design System (which has been described in several papers in the past) in conjunction with the Direct Release System provides machine designers with a fast, controlled environment for designing and releasing chip part numbers into East Fishkill and getting fast turnaround on newly designed chips for their engineering model machines. This paper describes how Programmers and Engineers at the East Fishkill facility solved the huge logistical and information management problems associated with handling the large volume of unique chip part numbers that are released into East Fishkill with requests for quick shipment of hardware at that released design level. The problems discussed involve providing accurate, timely manufacturing information, tracking the product in the line, and collecting/analyzing in-process and final test results for thousands of unique part numbers.
{"title":"Managing A Large Volume of Design/Manufacturing/Test Data in a Chip And Module Factory","authors":"V. J. Freund","doi":"10.1109/DAC.1984.1585835","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585835","url":null,"abstract":"In its highly automated East Fishkill semiconductor facility, IBM has exploited the \"gate array\" concept to its fullest in the support of computers designed using VLSI. IBM's Engineering Design System (which has been described in several papers in the past) in conjunction with the Direct Release System provides machine designers with a fast, controlled environment for designing and releasing chip part numbers into East Fishkill and getting fast turnaround on newly designed chips for their engineering model machines. This paper describes how Programmers and Engineers at the East Fishkill facility solved the huge logistical and information management problems associated with handling the large volume of unique chip part numbers that are released into East Fishkill with requests for quick shipment of hardware at that released design level. The problems discussed involve providing accurate, timely manufacturing information, tracking the product in the line, and collecting/analyzing in-process and final test results for thousands of unique part numbers.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"57 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123440877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The Magic VLSI layout editor contains an incremental design-rule checker. When the circuit is changed, only the modified areas are rechecked. The checker runs continuously in background to keep information about design-rule violations up-to-date. This paper describes the basic rule checker, which operates on edges in the layout, and the techniques used to perform incremental checking on hierarchical designs.
{"title":"Magic's Incremental Design-Rule Checker","authors":"G. Taylor, J. Ousterhout","doi":"10.5555/800033.800791","DOIUrl":"https://doi.org/10.5555/800033.800791","url":null,"abstract":"The Magic VLSI layout editor contains an incremental design-rule checker. When the circuit is changed, only the modified areas are rechecked. The checker runs continuously in background to keep information about design-rule violations up-to-date. This paper describes the basic rule checker, which operates on edges in the layout, and the techniques used to perform incremental checking on hierarchical designs.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"337 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122831713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/dac.1984.1585879
V. K. Raj, B. Pangrle, D. Gajski
The purpose of this paper is to describe a method for translating an instruction set described in a high level language into a register-transfer structure of a microprocessor. The designer interacts with the translator through the constraints imposed on the design, and by giving the initial but not necessarily complete description of the structure. A microinstruction table, which specifies the control sequence, as well as the datapath structure is the output of the translator.
{"title":"Microprocessor Synthesis","authors":"V. K. Raj, B. Pangrle, D. Gajski","doi":"10.1109/dac.1984.1585879","DOIUrl":"https://doi.org/10.1109/dac.1984.1585879","url":null,"abstract":"The purpose of this paper is to describe a method for translating an instruction set described in a high level language into a register-transfer structure of a microprocessor. The designer interacts with the translator through the constraints imposed on the design, and by giving the initial but not necessarily complete description of the structure. A microinstruction table, which specifies the control sequence, as well as the datapath structure is the output of the translator.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128356847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585888
Andrzej Wieclawski, M. Perkowski
The random logic portion of a chip Implementing a set of Boolean functions and sequential circuits usually represents a major contribution to chip area. Obviously, there are many circuits which realize the same Boolean function. Unfortunately, at present there is no general theory that provides designers (and design automation programs) with lower bounds for total area, for gate oxide area, and for delay time of logic Implementations in Integrated systems. Therefore, the main task for the computer optimization program appears In choice of the circuit with the most convenient layout. DIADES is a design automation system with register-transfer level description on its Input and CIF file on output [5]. The digital circuit can be described in both behavioral and structural mode. A set of successive compilations and hardware implementing and optimizing transformations create the description of the network on the level of logic gates and pass transistors. As the output of hardware compilation from the higher level, this description is usually nonoptimal and thus is next optimized by recursive technology independent transformations based on Boolean algebra (like A*O &equil; O, A*A &equil; A, etc.). Inverters are also inserted into long chains of AND or OR gates, being the results of iterative circuits' compilation [4]. The next stages are: technology dependant optimization of the logic network, and network's layout. It is assumed that the resultant network is multilevel, consists of complex negative gates, and is realized in semiregular Weinberger-style gate matrix layout. The logic minimization method intended for layout minimization is described in this paper. It is assumed in our silicon compiler, that logic is constructed of n-channel, polysilicon gate MOSFET ratioless complex gates, performing any negative function. By negative function we understand negation of positive function, while positive function is any combination of AND and OR functors [1]. Functions for evaluation of circuit's performance parameters such as total area, area of gate oxide, and gate delay time are used. These functions are defined in terms of basic technology and selected topology parameters. The method can be adapted to other technologies.
{"title":"Optimization of Negative Gate Networks Realized in Weinberger-Likf Layout in a Boolean Level Silicon Compiler","authors":"Andrzej Wieclawski, M. Perkowski","doi":"10.1109/DAC.1984.1585888","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585888","url":null,"abstract":"The random logic portion of a chip Implementing a set of Boolean functions and sequential circuits usually represents a major contribution to chip area. Obviously, there are many circuits which realize the same Boolean function. Unfortunately, at present there is no general theory that provides designers (and design automation programs) with lower bounds for total area, for gate oxide area, and for delay time of logic Implementations in Integrated systems. Therefore, the main task for the computer optimization program appears In choice of the circuit with the most convenient layout.\u0000 DIADES is a design automation system with register-transfer level description on its Input and CIF file on output [5]. The digital circuit can be described in both behavioral and structural mode. A set of successive compilations and hardware implementing and optimizing transformations create the description of the network on the level of logic gates and pass transistors. As the output of hardware compilation from the higher level, this description is usually nonoptimal and thus is next optimized by recursive technology independent transformations based on Boolean algebra (like A*O &equil; O, A*A &equil; A, etc.). Inverters are also inserted into long chains of AND or OR gates, being the results of iterative circuits' compilation [4].\u0000 The next stages are: technology dependant optimization of the logic network, and network's layout. It is assumed that the resultant network is multilevel, consists of complex negative gates, and is realized in semiregular Weinberger-style gate matrix layout. The logic minimization method intended for layout minimization is described in this paper.\u0000 It is assumed in our silicon compiler, that logic is constructed of n-channel, polysilicon gate MOSFET ratioless complex gates, performing any negative function. By negative function we understand negation of positive function, while positive function is any combination of AND and OR functors [1]. Functions for evaluation of circuit's performance parameters such as total area, area of gate oxide, and gate delay time are used. These functions are defined in terms of basic technology and selected topology parameters. The method can be adapted to other technologies.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121692978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585866
J. R. Dixon, M. K. Simmons, P. Cohen
An architecture for application of artificial intelligence to engineering design is presented and discussed. The architecture places emphasis on evaluation and redesign, thus reflecting the iterative nature of the design process. Six independent knowledge sources are included having the following functions: initial design, evaluation, acceptability decisions, redesign, user-designer input, and flow of control. A "blackboard" is used to store and exchange information among the knowledge sources. The implementation of the architecture is illustrated with two examples from the mechanical design domain: v-belt drives and extruded aluminum shapes.
{"title":"An Architecture for Application of Artificial Intelligence to Design","authors":"J. R. Dixon, M. K. Simmons, P. Cohen","doi":"10.1109/DAC.1984.1585866","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585866","url":null,"abstract":"An architecture for application of artificial intelligence to engineering design is presented and discussed. The architecture places emphasis on evaluation and redesign, thus reflecting the iterative nature of the design process. Six independent knowledge sources are included having the following functions: initial design, evaluation, acceptability decisions, redesign, user-designer input, and flow of control. A \"blackboard\" is used to store and exchange information among the knowledge sources. The implementation of the architecture is illustrated with two examples from the mechanical design domain: v-belt drives and extruded aluminum shapes.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127663275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585882
R. Kriete, R. K. Nettleton
A new methodology for designing VLSI circuits has been developed at Harris GSS. The methodology is based on the concept of parametric macro cells. A parametric macro cell is an MSI-level circuit which can be modified by a computer program to meet the needs of a particular design. In this paper we discuss the design methodology, chip layout, the simulation techniques and other software tools used to ensure a valid design, plus the water testing approach.
{"title":"A VLSI Design Methodology Based on Parametric Macro Cells","authors":"R. Kriete, R. K. Nettleton","doi":"10.1109/DAC.1984.1585882","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585882","url":null,"abstract":"A new methodology for designing VLSI circuits has been developed at Harris GSS. The methodology is based on the concept of parametric macro cells. A parametric macro cell is an MSI-level circuit which can be modified by a computer program to meet the needs of a particular design. In this paper we discuss the design methodology, chip layout, the simulation techniques and other software tools used to ensure a valid design, plus the water testing approach.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115380303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585785
C. Kingsley
This paper describes a compactor that is practical for compacting whole chips that are designed hierarchically, and can produce a reasonable result in spite of the layout being over-constrained. The layout produced is good enough to be used in high volume chips. The compactor is currently used in a cell layout system and a chip assembly tool.
{"title":"A Hiererachical, Error-Tolerant Compactor","authors":"C. Kingsley","doi":"10.1109/DAC.1984.1585785","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585785","url":null,"abstract":"This paper describes a compactor that is practical for compacting whole chips that are designed hierarchically, and can produce a reasonable result in spite of the layout being over-constrained. The layout produced is good enough to be used in high volume chips. The compactor is currently used in a cell layout system and a chip assembly tool.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129937124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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