Extracting designs of secure IPs using FPGA CAD tools

Abstract

In today's competitive market, a company's success is strongly dependent on delivering sophisticated and state-of-the-art IPs prior to their competitors. To take a short cut, a company may resort to reverse engineering or pirating their competitor's IP. In this paper, we examine the feasibility of extracting the design of a secure IP from one technology and using it in another. In particular, we start by extracting the IP from an FPGA vendor tool flow and map the IP blocks to an ASIC technology. We show that there is not a significant degradation in quality compared to starting with the original source, thus showing that taking a pirated IP from an FPGA and using it in another technology is viable, and therefore worth doing. This demonstrates a clear motivation for patching a vulnerability in FPGA CAD tools. Note that the intent of this work is not to promote the piracy of IPs. Instead, the goal is to demonstrate a mechanism for extracting a design as a means towards understanding what methods of pirating are possible, and whether they can be prevented.