Design of Multiple Prediction Complexity Configurations for an FPGA-Based H.264 Baseline Profile Encoder

Abstract

Video encoding has different methods and techniques in its implementation. Hardware implementations of video encoding systems are usually limited to a single set of compression techniques because of the trade-offs in area and power consumption. A workaround for this is through reconfigurable hardware devices such as the FPGA. The aim of this work is to use an FPGA to extend the set of compression techniques of an available video encoding system by changing the number of intra-prediction modes and motion estimation algorithm. Additionally, since the base system only caters to intra-prediction, an architectural design for the inter-prediction module with full-pixel resolution has been accomplished. The addition of intra-prediction modes showed a very minimal decrease in the total encoding time. This, however, showed 0.44% increase in the resource utilization. The different search algorithms used manifested the expected highest to lowest execution time respectively. The trade-off of higher PSNR versus longer encoding time was shown. An average of 76.96% decrease in execution time was observed while achieving a 0.27% decrease in PSNR.