Analysis and Hardware Optimization of Lattice Post-Quantum Cryptography Workloads

Sandhya Koteshwara, M. Kumar, P. Pattnaik
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Abstract

The mathematical constructs, nature of computations and challenges in optimizing lattice post-quantum cryptographic algorithms on modern many-core processors are discussed in this paper. Identification of time-consuming functions and subsequent hardware optimization using vector units and hardware accelerators of one of the candidates, CRYSTALS-Kyber, leads to performance improvement of around 52% for its SHA3 variant and 83% for its AES variant. Detailed Cycles-per-Instruction (CPI) stack breakdown before and after optimization indicates a CPI of around 0.5 and dominance of load/store operations in these workloads.
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点阵后量子加密工作负载分析与硬件优化
本文讨论了在现代多核处理器上优化格子后量子密码算法的数学结构、计算性质和挑战。使用其中一个候选算法CRYSTALS-Kyber的矢量单元和硬件加速器识别耗时的函数和随后的硬件优化,使其SHA3变体的性能提高了约52%,AES变体的性能提高了83%。优化前后的每条指令周期(Cycles-per-Instruction, CPI)堆栈详细细分表明,CPI约为0.5,并且在这些工作负载中负载/存储操作占主导地位。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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Analysis and Hardware Optimization of Lattice Post-Quantum Cryptography Workloads Position Paper: Consider Hardware-enhanced Defenses for Rootkit Attacks Uncovering Hidden Instructions in Armv8-A Implementations Implementing the Draft RISC-V Scalar Cryptography Extensions Position Paper:Defending Direct Memory Access with CHERI Capabilities
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