Design of a robust and ultra-low-voltage pulse-triggered flip-flop in 28nm UTBB-FDSOI technology

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2013-10-01 DOI:10.1109/S3S.2013.6716555

Sebastien Bernard, A. Valentian, M. Belleville, D. Bol, J. Legat

引用次数: 0

Abstract

So far, pulse-triggered flip-flops (pulsed-FFs) are mainly used in high-performance digital circuits, thanks to their small data-to-output delay. However, they suffer from a poor robustness to local variations occurring at ultra-low-voltage (ULV). Thanks to an innovative pulse generator, the operability of an energy-efficient pulsed-FF was validated at ultra-low operating supply voltage. Measurements of delays and correct functionality are performed in 28nm FDSOI technology. Then, the effect of back bias voltage, a key point in FDSOI technology, is studied and it is shown that our pulsed-FF reaches a minimum operating supply voltage of 170mV.

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基于28nm UTBB-FDSOI技术的稳健性超低电压脉冲触发触发器设计

到目前为止，脉冲触发触发器(pulse - ff)主要用于高性能数字电路，因为它们的数据到输出延迟小。然而，它们对超低电压(ULV)下发生的局部变化具有较差的鲁棒性。由于采用了创新的脉冲发生器，节能脉冲式ff在超低工作电源电压下的可操作性得到了验证。延迟和正确功能的测量在28nm FDSOI技术中进行。然后，研究了反向偏置电压对FDSOI技术的影响，结果表明，我们的脉冲ff达到了170mV的最小工作电源电压。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

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