{"title":"A Comparison between Single Purpose and Flexible Neuromorphic Processor Designs","authors":"D. Mountain, Mark McLean, Christopher D. Krieger","doi":"10.1109/ICRC.2017.8123641","DOIUrl":null,"url":null,"abstract":"A variety of architectures have been proposed for neuromorphic computing chips, including digital, analog, and memristor based approaches. The application space used to analyze these designs is typically narrow, focused primarily on natural signal processing tasks such as image or audio classification. In this work, we analyze the ability of a memristor-based neuromorphic architecture to perform tasks representative of those done by computer network edge devices. We evaluate the neuromorphic designs running a baseline benchmark (MNIST), an AES-256 encryptor, and a malware detection tool. We evaluate these applications on both single purpose chips and on flexible multipurpose chips configured for the same tasks. Single purpose designs use direct, hardwired connections and custom memristor crossbar sizes, while flexible designs use crossbar arrays of a single standard size and communicate over an on-chip network. The throughput per watt and throughput per area costs associated with increased flexibility are shown to be 1.8x and 8x-10x, respectively.","PeriodicalId":125114,"journal":{"name":"2017 IEEE International Conference on Rebooting Computing (ICRC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE International Conference on Rebooting Computing (ICRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICRC.2017.8123641","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A variety of architectures have been proposed for neuromorphic computing chips, including digital, analog, and memristor based approaches. The application space used to analyze these designs is typically narrow, focused primarily on natural signal processing tasks such as image or audio classification. In this work, we analyze the ability of a memristor-based neuromorphic architecture to perform tasks representative of those done by computer network edge devices. We evaluate the neuromorphic designs running a baseline benchmark (MNIST), an AES-256 encryptor, and a malware detection tool. We evaluate these applications on both single purpose chips and on flexible multipurpose chips configured for the same tasks. Single purpose designs use direct, hardwired connections and custom memristor crossbar sizes, while flexible designs use crossbar arrays of a single standard size and communicate over an on-chip network. The throughput per watt and throughput per area costs associated with increased flexibility are shown to be 1.8x and 8x-10x, respectively.