Pub Date : 2017-11-28DOI: 10.1109/ICRC.2017.8123649
P. Bruel, S. R. Chalamalasetti, Chris I. Dalton, I. E. Hajj, A. Goldman, Catherine E. Graves, Wen-mei W. Hwu, Phil Laplante, D. Milojicic, Geoffrey Ndu, J. Strachan
The deceleration of transistor feature size scaling has motivated growing adoption of specialized accelerators implemented as GPUs, FPGAs, ASICs, and more recently new types of computing such as neuromorphic, bio-inspired, ultra low energy, reversible, stochastic, optical, quantum, combinations, and others unforeseen. There is a tension between specialization and generalization, with the current state trending to master slave models where accelerators (slaves) are instructed by a general purpose system (master) running an Operating System (OS). Traditionally, an OS is a layer between hardware and applications and its primary function is to manage hardware resources and provide a common abstraction to applications. Does this function, however, apply to new types of computing paradigms? This paper revisits OS functionality for memristor-based accelerators. We explore one accelerator implementation, the Dot Product Engine (DPE), for a select pattern of applications in machine learning, imaging, and scientific computing and a small set of use cases. We explore typical OS functionality, such as reconfiguration, partitioning, security, virtualization, and programming. We also explore new types of functionality, such as precision and trustworthiness of reconfiguration. We claim that making an accelerator, such as the DPE, more general will result in broader adoption and better utilization.
{"title":"Generalize or Die: Operating Systems Support for Memristor-Based Accelerators","authors":"P. Bruel, S. R. Chalamalasetti, Chris I. Dalton, I. E. Hajj, A. Goldman, Catherine E. Graves, Wen-mei W. Hwu, Phil Laplante, D. Milojicic, Geoffrey Ndu, J. Strachan","doi":"10.1109/ICRC.2017.8123649","DOIUrl":"https://doi.org/10.1109/ICRC.2017.8123649","url":null,"abstract":"The deceleration of transistor feature size scaling has motivated growing adoption of specialized accelerators implemented as GPUs, FPGAs, ASICs, and more recently new types of computing such as neuromorphic, bio-inspired, ultra low energy, reversible, stochastic, optical, quantum, combinations, and others unforeseen. There is a tension between specialization and generalization, with the current state trending to master slave models where accelerators (slaves) are instructed by a general purpose system (master) running an Operating System (OS). Traditionally, an OS is a layer between hardware and applications and its primary function is to manage hardware resources and provide a common abstraction to applications. Does this function, however, apply to new types of computing paradigms? This paper revisits OS functionality for memristor-based accelerators. We explore one accelerator implementation, the Dot Product Engine (DPE), for a select pattern of applications in machine learning, imaging, and scientific computing and a small set of use cases. We explore typical OS functionality, such as reconfiguration, partitioning, security, virtualization, and programming. We also explore new types of functionality, such as precision and trustworthiness of reconfiguration. We claim that making an accelerator, such as the DPE, more general will result in broader adoption and better utilization.","PeriodicalId":125114,"journal":{"name":"2017 IEEE International Conference on Rebooting Computing (ICRC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123434510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICRC.2017.8123654
Georg Hahn, H. Djidjev
Recent advances in the development of commercial quantum annealers such as the D-Wave 2X allow solving NP-hard optimization problems that can be expressed as quadratic unconstrained binary programs. However, the relatively small number of available qubits (around 1000 for the D-Wave 2X quantum annealer) poses a severe limitation to the range of problems that can be solved. This paper explores the suitability of preprocessing methods for reducing the sizes of the input programs and thereby the number of qubits required for their solution on quantum computers. Such methods allow us to determine the value of certain variables that hold in either any optimal solution (called strong persistencies) or in at least one optimal solution (weak persistencies). We investigate preprocessing methods for two important NP-hard graph problems, the computation of a maximum clique and a maximum cut in a graph. We show that the identification of strong and weak persistencies for those two optimization problems is very instance-specific,but can lead to substantial reductions in the number of variables.
{"title":"Reducing Binary Quadratic Forms for More Scalable Quantum Annealing","authors":"Georg Hahn, H. Djidjev","doi":"10.1109/ICRC.2017.8123654","DOIUrl":"https://doi.org/10.1109/ICRC.2017.8123654","url":null,"abstract":"Recent advances in the development of commercial quantum annealers such as the D-Wave 2X allow solving NP-hard optimization problems that can be expressed as quadratic unconstrained binary programs. However, the relatively small number of available qubits (around 1000 for the D-Wave 2X quantum annealer) poses a severe limitation to the range of problems that can be solved. This paper explores the suitability of preprocessing methods for reducing the sizes of the input programs and thereby the number of qubits required for their solution on quantum computers. Such methods allow us to determine the value of certain variables that hold in either any optimal solution (called strong persistencies) or in at least one optimal solution (weak persistencies). We investigate preprocessing methods for two important NP-hard graph problems, the computation of a maximum clique and a maximum cut in a graph. We show that the identification of strong and weak persistencies for those two optimization problems is very instance-specific,but can lead to substantial reductions in the number of variables.","PeriodicalId":125114,"journal":{"name":"2017 IEEE International Conference on Rebooting Computing (ICRC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124857123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICRC.2017.8123665
Stewart Allen, Jungsang Kim, D. Moehring, C. Monroe
We present progress on the construction and operation of a room- temperature quantum computer built with trapped atomic ion qubits. Based on the technological underpinnings of atomic clocks that define time, atomic qubits are standards of quantum information because they are all identical. They present a fundamentally scalable approach to quantum computation where interactions can be faithfully replicated and measured with near-perfect efficiency. Moreover, the connection among atomic ion qubits are forged from external laser beams and mediated by the Coulomb repulsion between them, and hence behave as a fully reconfigurable quantum circuit, much like an FPGA in classical computation. We further discuss paths to scaling using demonstrated technologies that are unique to this class of quantum computation devices. This flexibility will likely allow ion trap quantum computers to express the superset of all known quantum computation operations, and thus efficiently target any type of application that arises.
{"title":"Reconfigurable and Programmable Ion Trap Quantum Computer","authors":"Stewart Allen, Jungsang Kim, D. Moehring, C. Monroe","doi":"10.1109/ICRC.2017.8123665","DOIUrl":"https://doi.org/10.1109/ICRC.2017.8123665","url":null,"abstract":"We present progress on the construction and operation of a room- temperature quantum computer built with trapped atomic ion qubits. Based on the technological underpinnings of atomic clocks that define time, atomic qubits are standards of quantum information because they are all identical. They present a fundamentally scalable approach to quantum computation where interactions can be faithfully replicated and measured with near-perfect efficiency. Moreover, the connection among atomic ion qubits are forged from external laser beams and mediated by the Coulomb repulsion between them, and hence behave as a fully reconfigurable quantum circuit, much like an FPGA in classical computation. We further discuss paths to scaling using demonstrated technologies that are unique to this class of quantum computation devices. This flexibility will likely allow ion trap quantum computers to express the superset of all known quantum computation operations, and thus efficiently target any type of application that arises.","PeriodicalId":125114,"journal":{"name":"2017 IEEE International Conference on Rebooting Computing (ICRC)","volume":"1873 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128684776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICRC.2017.8123633
R. Meeson
We describe an effort to simulate the neural pathway from the inner ear (cochlea) to the primary auditory cortex in the brain. The human cochlea contains sensory cells (inner hair cells), which respond to the mechanical motion of traveling waves that sweep along the basilar membrane. Neurons triggered by the sensory cells carry sound signals from the cochlea to the brain through a series of a half-dozen transfer sites. At each junction, firing neurons stimulate some and inhibit other neighboring neurons. The signal processing effects of these interactions are not fully understood. The net behavior is difficult to observe in-vivo because the neurons are not easily accessible and only a relatively few can be measured at one time. As a result, the "neural code" that represents sound signals is not understood. We do know, however, that our perception of sound is much more refined than the signal observable at the cochlea. Frequencies are only broadly separated within the cochlea, for example, yet we are able to perceive very narrow differences in pitch. The simulation model we are constructing provides a means to fully instrument all of the neurons and their interactions. The model allows for a wide range of signal analysis experimentation, which we hope will help untangle how this neural processing works.
{"title":"Auditory Neural Pathway Simulation","authors":"R. Meeson","doi":"10.1109/ICRC.2017.8123633","DOIUrl":"https://doi.org/10.1109/ICRC.2017.8123633","url":null,"abstract":"We describe an effort to simulate the neural pathway from the inner ear (cochlea) to the primary auditory cortex in the brain. The human cochlea contains sensory cells (inner hair cells), which respond to the mechanical motion of traveling waves that sweep along the basilar membrane. Neurons triggered by the sensory cells carry sound signals from the cochlea to the brain through a series of a half-dozen transfer sites. At each junction, firing neurons stimulate some and inhibit other neighboring neurons. The signal processing effects of these interactions are not fully understood. The net behavior is difficult to observe in-vivo because the neurons are not easily accessible and only a relatively few can be measured at one time. As a result, the \"neural code\" that represents sound signals is not understood. We do know, however, that our perception of sound is much more refined than the signal observable at the cochlea. Frequencies are only broadly separated within the cochlea, for example, yet we are able to perceive very narrow differences in pitch. The simulation model we are constructing provides a means to fully instrument all of the neurons and their interactions. The model allows for a wide range of signal analysis experimentation, which we hope will help untangle how this neural processing works.","PeriodicalId":125114,"journal":{"name":"2017 IEEE International Conference on Rebooting Computing (ICRC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130471968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICRC.2017.8123668
Yangjie Qi, Raqibul Hasan, Rasitha Fernando, T. Taha
Compact online learning architectures could be used to enhance internet of things devices to allow them to learn directly based on data being received instead of having to ship data to a remote server for learning. This saves communications energy and enhances privacy and security as the data is not shared. The learning architectures can also be used in high performance computing and in traditional computing architectures to learn approximations of the functions being performed based on runtime activities. This paper presents the Socrates-D a digital multicore on-chip learning architecture for deep neural networks. It has memories internal to each neural core to store synaptic weights. A variety of deep learning applications can be processed in this architecture. The system level area and power benefits of the specialized architecture is compared with an NVIDIA GEFORCE GTX 980Ti GPGPU. Our experimental evaluations show that the proposed architecture can provide significant area and energy efficiencies over GPGPUs for both training and inference.
{"title":"Socrates-D: Multicore Architecture for On-Line Learning","authors":"Yangjie Qi, Raqibul Hasan, Rasitha Fernando, T. Taha","doi":"10.1109/ICRC.2017.8123668","DOIUrl":"https://doi.org/10.1109/ICRC.2017.8123668","url":null,"abstract":"Compact online learning architectures could be used to enhance internet of things devices to allow them to learn directly based on data being received instead of having to ship data to a remote server for learning. This saves communications energy and enhances privacy and security as the data is not shared. The learning architectures can also be used in high performance computing and in traditional computing architectures to learn approximations of the functions being performed based on runtime activities. This paper presents the Socrates-D a digital multicore on-chip learning architecture for deep neural networks. It has memories internal to each neural core to store synaptic weights. A variety of deep learning applications can be processed in this architecture. The system level area and power benefits of the specialized architecture is compared with an NVIDIA GEFORCE GTX 980Ti GPGPU. Our experimental evaluations show that the proposed architecture can provide significant area and energy efficiencies over GPGPUs for both training and inference.","PeriodicalId":125114,"journal":{"name":"2017 IEEE International Conference on Rebooting Computing (ICRC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127607565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICRC.2017.8123669
S. Srikanth, T. Conte, E. Debenedictis, Jeanine E. Cook
We present a new non-von Neumann architecture, termed "Superstrider," predicated on no more than current projected improvements in semiconductor components and 3D manufacturing technologies, which should offer orders of magnitude advances in both energy efficiency and performance for many high-utility problem classes. The architecture is described, which is based on computing on row-wide memory words to accelerate sparse matrix algebraic operations that are normally implemented as scalar operations. A cycle-accurate simulation demonstrates potential performance improvements on existing High Bandwidth Memory (HBM) on the order of 50× that increases to 1000× or more when implemented using a fully integrated 3D technology and compared to a simple baseline. Further refinement may change these numbers, but the magnitude of the opportunity suggests further work.
{"title":"The Superstrider Architecture: Integrating Logic and Memory Towards Non-Von Neumann Computing","authors":"S. Srikanth, T. Conte, E. Debenedictis, Jeanine E. Cook","doi":"10.1109/ICRC.2017.8123669","DOIUrl":"https://doi.org/10.1109/ICRC.2017.8123669","url":null,"abstract":"We present a new non-von Neumann architecture, termed \"Superstrider,\" predicated on no more than current projected improvements in semiconductor components and 3D manufacturing technologies, which should offer orders of magnitude advances in both energy efficiency and performance for many high-utility problem classes. The architecture is described, which is based on computing on row-wide memory words to accelerate sparse matrix algebraic operations that are normally implemented as scalar operations. A cycle-accurate simulation demonstrates potential performance improvements on existing High Bandwidth Memory (HBM) on the order of 50× that increases to 1000× or more when implemented using a fully integrated 3D technology and compared to a simple baseline. Further refinement may change these numbers, but the magnitude of the opportunity suggests further work.","PeriodicalId":125114,"journal":{"name":"2017 IEEE International Conference on Rebooting Computing (ICRC)","volume":"219 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122254536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICRC.2017.8123653
N. T. Nguyen, Amy E. Larson, Garrett T. Kenyon
We use a quantum annealing D-Wave 2X (1,152-qubit) computer to generate sparse representations of Canny-filtered, center-cropped 30x30 CIFAR-10 images. Each binary neuron (qubit) represents a feature kernel obtained initially by imprinting on a randomly chosen 5x5 image patch and then adapted via an off-line Hebbian learning protocol using the sparse solutions generated by the D-Wave. When using binary neurons, the energy function is non-convex (multiple local-minima) and finding a global minimum is NP-hard. Quantum annealing provides a strategy for finding sparse representations that correspond to good local minima of a non-convex cost function. To overcome the severe coupling restrictions between physical qubits on the D-Wave Chimera graph, we use embedding tools to achieve approximately all-to-all connectivity across a reduced number of logical qubits. We assess the sparse representations generated by the D-Wave using both the total energy as well as classification accuracy on a subset of the CIFAR-10 database. The D-Wave 2X outperforms two classical state-of-the-art binary solvers, GUROBI and Chimera-inspired algorithm Hamze-Freitas-Selby (HFS). Specifically, the D-Wave 2X yields lower energy sparse solutions within seconds while the largest problems take over 10 hours for both GUROBI and HFS. We obtained cross-validation classification of 31.02% for the first 4K images using 47 features on the quantum D- Wave 2X.
{"title":"Generating Sparse Representations Using Quantum Annealing: Comparison to Classical Algorithms","authors":"N. T. Nguyen, Amy E. Larson, Garrett T. Kenyon","doi":"10.1109/ICRC.2017.8123653","DOIUrl":"https://doi.org/10.1109/ICRC.2017.8123653","url":null,"abstract":"We use a quantum annealing D-Wave 2X (1,152-qubit) computer to generate sparse representations of Canny-filtered, center-cropped 30x30 CIFAR-10 images. Each binary neuron (qubit) represents a feature kernel obtained initially by imprinting on a randomly chosen 5x5 image patch and then adapted via an off-line Hebbian learning protocol using the sparse solutions generated by the D-Wave. When using binary neurons, the energy function is non-convex (multiple local-minima) and finding a global minimum is NP-hard. Quantum annealing provides a strategy for finding sparse representations that correspond to good local minima of a non-convex cost function. To overcome the severe coupling restrictions between physical qubits on the D-Wave Chimera graph, we use embedding tools to achieve approximately all-to-all connectivity across a reduced number of logical qubits. We assess the sparse representations generated by the D-Wave using both the total energy as well as classification accuracy on a subset of the CIFAR-10 database. The D-Wave 2X outperforms two classical state-of-the-art binary solvers, GUROBI and Chimera-inspired algorithm Hamze-Freitas-Selby (HFS). Specifically, the D-Wave 2X yields lower energy sparse solutions within seconds while the largest problems take over 10 hours for both GUROBI and HFS. We obtained cross-validation classification of 31.02% for the first 4K images using 47 features on the quantum D- Wave 2X.","PeriodicalId":125114,"journal":{"name":"2017 IEEE International Conference on Rebooting Computing (ICRC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114762395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICRC.2017.8123663
P. Civalleri, F. Corinto, Á. Csurgay
The physical constraints underlying the concept of quantum circuit are considered. In particular it is shown that the point of departure for their modeling starts from the interconnection of the components into a classical network, followed by quantization of the latter, and not by the interconnection of already quantized components. The procedure is straightforward for lossless networks but cannot be worked out in presence of resistors for the impossibility of constructing a Lagrangian function. However the difficulty is circumvented by distinguishing thermal from radiative resistors, the former being the usual ones, the latter being realized by semi-infinite LC transmission lines, for which the Lagrangian exists. In the complex plane s = σ + jω the impedance of a thermal resistor is Z(s) = R in the entire plane while that of a radiative resistor is Rsign(σ), so that the latter is lossless and does not dissipate energy but conveys it to the infinity. Comparison with Lindblad approach shows that the resistor fits into it in the RHP. Radiative resistors make evolution reversible, which is not true for a physical system including thermal.
{"title":"Physical Constraints on Quantum Circuits","authors":"P. Civalleri, F. Corinto, Á. Csurgay","doi":"10.1109/ICRC.2017.8123663","DOIUrl":"https://doi.org/10.1109/ICRC.2017.8123663","url":null,"abstract":"The physical constraints underlying the concept of quantum circuit are considered. In particular it is shown that the point of departure for their modeling starts from the interconnection of the components into a classical network, followed by quantization of the latter, and not by the interconnection of already quantized components. The procedure is straightforward for lossless networks but cannot be worked out in presence of resistors for the impossibility of constructing a Lagrangian function. However the difficulty is circumvented by distinguishing thermal from radiative resistors, the former being the usual ones, the latter being realized by semi-infinite LC transmission lines, for which the Lagrangian exists. In the complex plane s = σ + jω the impedance of a thermal resistor is Z(s) = R in the entire plane while that of a radiative resistor is Rsign(σ), so that the latter is lossless and does not dissipate energy but conveys it to the infinity. Comparison with Lindblad approach shows that the resistor fits into it in the RHP. Radiative resistors make evolution reversible, which is not true for a physical system including thermal.","PeriodicalId":125114,"journal":{"name":"2017 IEEE International Conference on Rebooting Computing (ICRC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114973481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICRC.2017.8123647
Dillon Graham, Seyed Hamed Fatemi Langroudi, Christopher Kanan, D. Kudithipudi
Analyzing spatio-temporal data like video is a challenging task that requires processing visual and temporal information effectively. Convolutional Neural Networks have shown promise as baseline fixed feature extractors through transfer learning, a technique that helps minimize the training cost on visual information. Temporal information is often handled using hand-crafted features or Recurrent Neural Networks, but this can be overly specific or prohibitively complex. Building a fully trainable system that can efficiently analyze spatio-temporal data without hand-crafted features or complex training is an open challenge. We present a new neural network architecture to address this challenge, the Convolutional Drift Network (CDN). Our CDN architecture combines the visual feature extraction power of deep Convolutional Neural Networks with the intrinsically efficient temporal processing provided by Reservoir Computing. In this introductory paper on the CDN, we provide a very simple baseline implementation tested on two egocentric (first-person) video activity datasets. We achieve video-level activity classification results on-par with state-of-the art methods. Notably, performance on this complex spatio- temporal task was produced by only training a single feed-forward layer in the CDN.
{"title":"Convolutional Drift Networks for Video Classification","authors":"Dillon Graham, Seyed Hamed Fatemi Langroudi, Christopher Kanan, D. Kudithipudi","doi":"10.1109/ICRC.2017.8123647","DOIUrl":"https://doi.org/10.1109/ICRC.2017.8123647","url":null,"abstract":"Analyzing spatio-temporal data like video is a challenging task that requires processing visual and temporal information effectively. Convolutional Neural Networks have shown promise as baseline fixed feature extractors through transfer learning, a technique that helps minimize the training cost on visual information. Temporal information is often handled using hand-crafted features or Recurrent Neural Networks, but this can be overly specific or prohibitively complex. Building a fully trainable system that can efficiently analyze spatio-temporal data without hand-crafted features or complex training is an open challenge. We present a new neural network architecture to address this challenge, the Convolutional Drift Network (CDN). Our CDN architecture combines the visual feature extraction power of deep Convolutional Neural Networks with the intrinsically efficient temporal processing provided by Reservoir Computing. In this introductory paper on the CDN, we provide a very simple baseline implementation tested on two egocentric (first-person) video activity datasets. We achieve video-level activity classification results on-par with state-of-the art methods. Notably, performance on this complex spatio- temporal task was produced by only training a single feed-forward layer in the CDN.","PeriodicalId":125114,"journal":{"name":"2017 IEEE International Conference on Rebooting Computing (ICRC)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122116796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICRC.2017.8123686
Chen Yan, E. Salman
According to International Roadmap for Devices and Systems (IRDS), after 2024, there is no headroom for 2D geometry scaling. By 2024, IRDS predicts that monolithic 3D integration technology will be one of the most critical performance boosters. This prediction follows the highly promising and relatively recent improvements on the fabrication of second-tier devices on a single substrate. In this study, a fully functional and open source cell library is developed to design and characterize large-scale monolithic 3D ICs. The second version of the 3D cell library is equipped with the required files for integration into existing design automation tools, thereby enabling chip-level benchmarking. Furthermore, multiple versions of the library are proposed to investigate the tradeoffs among routability, timing, power, and area characteristics. The 3D library can also be used to analyze some of the important issues in monolithic 3D ICs, such as chip-level thermal characteristics, efficacy of various thermal management methodologies, and design-for-test methods for monolithic 3D integration.
{"title":"Routing Congestion Aware Cell Library Development for Monolithic 3D ICs","authors":"Chen Yan, E. Salman","doi":"10.1109/ICRC.2017.8123686","DOIUrl":"https://doi.org/10.1109/ICRC.2017.8123686","url":null,"abstract":"According to International Roadmap for Devices and Systems (IRDS), after 2024, there is no headroom for 2D geometry scaling. By 2024, IRDS predicts that monolithic 3D integration technology will be one of the most critical performance boosters. This prediction follows the highly promising and relatively recent improvements on the fabrication of second-tier devices on a single substrate. In this study, a fully functional and open source cell library is developed to design and characterize large-scale monolithic 3D ICs. The second version of the 3D cell library is equipped with the required files for integration into existing design automation tools, thereby enabling chip-level benchmarking. Furthermore, multiple versions of the library are proposed to investigate the tradeoffs among routability, timing, power, and area characteristics. The 3D library can also be used to analyze some of the important issues in monolithic 3D ICs, such as chip-level thermal characteristics, efficacy of various thermal management methodologies, and design-for-test methods for monolithic 3D integration.","PeriodicalId":125114,"journal":{"name":"2017 IEEE International Conference on Rebooting Computing (ICRC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121236192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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