{"title":"Methodology for process portable hard IP block creation using cell based array architecture","authors":"R. Gopisetty, K. Hsu, A. Chakankar","doi":"10.1109/ASIC.1998.722992","DOIUrl":null,"url":null,"abstract":"A methodology for hard IP creation and an automated \"process tuned\" migration of this IP block is presented. The flow for hard IP creation using the CBA Block Export Flow is presented. Salient features of this include automated IP block timing model creation and physical view creation allowing easy encapsulation of the IP core into a chip level environment. Following this, a flow for automatically porting this IP core so that it is optimally implemented in the target process using CBA Block Transport is presented.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1998.722992","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A methodology for hard IP creation and an automated "process tuned" migration of this IP block is presented. The flow for hard IP creation using the CBA Block Export Flow is presented. Salient features of this include automated IP block timing model creation and physical view creation allowing easy encapsulation of the IP core into a chip level environment. Following this, a flow for automatically porting this IP core so that it is optimally implemented in the target process using CBA Block Transport is presented.
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