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Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)最新文献

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Analog And Mixed-signal 模拟和混合信号
Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722796
M. Gaboury, P. R. Mukund
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引用次数: 5
Design of standard cells used in low-power ASIC's exploiting the multiple-supply-voltage scheme 采用多电源电压方案的低功耗ASIC标准单元的设计
Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722815
Jinn-Shyan Wang, Shang-Jyh Shieh, J. Wang, C. Yeh
ASIC design utilizing the multiple-supply-voltage (MSV) scheme has been shown to be efficient in reducing the power consumption. A new layout style of standard cells to be used in ASIC designs is proposed to effectively exploit the advantages afforded by the MSV scheme. Each standard cell is designed to use two power rails that are fed with different supply voltages. Then, the cells can be butted together arbitrarily no matter whether the cells are supplied from a high or low voltage, and the existing P&R tool can place and route the circuit as usual. As compared to the design with only one supply voltage, the average saving of power consumption of the new design (using the new cells and adopting the MSV scheme) is over 30%, but the average area overhead is only about 8%. Meanwhile, the average interconnection length is only increased by about 7.5%.
采用多电源电压(MSV)方案的ASIC设计已被证明在降低功耗方面是有效的。为了有效地利用MSV方案的优点,提出了一种新的用于ASIC设计的标准单元布局样式。每个标准电池被设计成使用两个电源轨,这些电源轨有不同的供电电压。然后,无论电池是由高电压还是低电压供电,电池都可以任意地连接在一起,现有的P&R工具可以像往常一样放置和布线电路。与只有一个电源电压的设计相比,新设计(使用新电池并采用MSV方案)的功耗平均节省30%以上,而平均面积开销仅为8%左右。与此同时,平均互连长度仅增加了7.5%左右。
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引用次数: 20
A 10 b 20-Msample/s 28 mW CMOS ADC in ASIC process ASIC制程的10b20mps 28mw CMOS ADC
Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722803
A. Wada, K. Tani, Y. Matsushita, Y. Harada
We have developed a 20 Msample/s 10 b CMOS ADC with a 2.4 V power supply, in 0.35 /spl mu/m 1-poly 2-Metal ASIC process without a special analog process, which is suitable for embedding in ASICs because of the small area (4.84 mm/sup 2/) and small power consumption. To realize this ADC we have developed a 2-step interstage amplifying pipeline system and new circuit technologies for residue amplifiers. The prototype chip was fabricated and was measured. It shows good linearity of less than /spl plusmn/1 LSB and 28 mW power consumption with 2.4 V at 20 MHz sampling.
我们在0.35 /spl mu/m 1-poly - metal ASIC工艺中开发了一个20 Msample/s的10 b CMOS ADC,电源为2.4 V,无需特殊的模拟工艺,由于面积小(4.84 mm/sup 2/),功耗小,适合嵌入ASIC中。为了实现这个ADC,我们开发了一个两级间放大管道系统和新的剩余放大器电路技术。制作了原型芯片并进行了测试。它显示出良好的线性度,小于/spl plusmn/1 LSB,功耗为28 mW,采样频率为2.4 V,采样频率为20 MHz。
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引用次数: 0
Dynamic circuit synthesis using the Owens tool set 动态电路合成使用欧文斯工具集
Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722903
M. J. Irwin, R.Y. Chen
This paper overviews the Owens CAD tool set developed at Penn State University and illustrates its ability to synthesize dynamic CMOS circuits. The CAD system includes: a cell compiler with transistor sizing and I/O direction annotation; a simulation tool based on the switch-level logic model; tools for multi-level logic optimization; and tools for format conversion which establish a connection with the netlist specification, truth tables, Boolean equations and VHDL. The Owens tool set is able to implement various CMOS structures such as static gates, dynamic gates and transmission gates. In particular, since it supports transistor sizing, it creates an efficient design environment for dynamic circuit implementation and optimization. To show this feature, this paper illustrates the application of the Owens tool set to the design of zipper CMOS adders and Manchester carry chain adders which are typical dynamic circuits.
本文概述了宾夕法尼亚州立大学开发的Owens CAD工具集,并说明了其合成动态CMOS电路的能力。该CAD系统包括:具有晶体管尺寸和I/O方向标注的单元编译器;基于开关级逻辑模型的仿真工具多级逻辑优化工具;以及用于格式转换的工具,这些工具与网表规范、真值表、布尔方程和VHDL建立了连接。Owens工具集能够实现各种CMOS结构,如静态门,动态门和传输门。特别是,由于它支持晶体管尺寸,它为动态电路实现和优化创造了一个有效的设计环境。为了说明这一特点,本文举例说明了Owens工具集在拉链CMOS加法器和曼切斯特进位链加法器这两种典型动态电路设计中的应用。
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引用次数: 3
Designing a Java microprocessor core using FPGA technology 利用FPGA技术设计一个Java微处理器内核
Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722787
A. Kim, M. Chang
Ever since its introduction from Sun Microsystems three years ago, Java has been widely accepted in the computing and Internet industry. However the run-time performance is still not good enough for Java to become a general purpose programming language. This paper shows how to implement a Java microprocessor core in silicon to speed up the execution of Java. For a reconfigurable and flexible design, the Field Programmable Gate Array (FPGA) is chosen as a target technology for the Java microprocessor. By applying a top-down hardware design methodology to the FPGA design process, it becomes easier and more flexible to implement Java in a FPGA. The DFT technique is added for better testability.
自从三年前由Sun Microsystems公司推出以来,Java已经在计算和互联网行业中被广泛接受。然而,运行时性能仍然不足以使Java成为一种通用编程语言。本文介绍了如何在硅片上实现一个Java微处理器内核,以提高Java的执行速度。为了实现可重构和灵活的设计,本文选择现场可编程门阵列(FPGA)作为Java微处理器的目标技术。通过将自顶向下的硬件设计方法应用于FPGA设计过程,在FPGA中实现Java变得更加容易和灵活。为了更好的可测试性,添加了DFT技术。
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引用次数: 15
The improvement of conditional sum adder for low power applications 低功耗条件加法器的改进
Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722817
Kuo-Hsing Cheng, Shu-Min Chiang, Shun-Wen Cheng
The authors describe a new conditional-sum rule for low power applications. This conditional sum adder is especially attractive for implementing high-speed arithmetic systems. The new conditional sum addition rule can reduce the internal nodes and multiplexer numbers of the adder design. Various supply voltages and circuit structures are used to implement the new conditional sum adders. It is shown that about 10% to 25% power-delay product is saved.
作者描述了一种新的低功耗应用条件和规则。这种条件加法器对实现高速算术系统特别有吸引力。新的条件和加法规则可以减少加法器设计中的内部节点和多路器数量。使用不同的电源电压和电路结构来实现新的条件加法器。结果表明,可节省约10% ~ 25%的功率延迟产品。
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引用次数: 12
CMOS-based sensors and actuators 基于cmos的传感器和执行器
Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.723047
F. Van Steenkiste, D. Maes, L. Haspeslagh, S. Sedky, P. Van Gerwen, S. Vandergroen, K. Baert
In many applications, up to millions of sensors or actuators have to be connected to the outside world, making the monolithic integration of circuits mandatory. Monolithic integration is also pursued for mass-produced transducers. Today, monolithic devices include visible and IR imagers, displays, inkjet heads, biochemical and physical sensors. Monolithic integration of transducer-specific processes (such as micromachining) with standard CMOS processes is possible, albeit at an increase of process complexity.
在许多应用中,多达数百万个传感器或执行器必须连接到外部世界,这使得电路的单片集成成为必要。大规模生产的换能器也追求单片集成。如今,单片器件包括可见光和红外成像仪、显示器、喷墨头、生化和物理传感器。传感器特定工艺(如微加工)与标准CMOS工艺的单片集成是可能的,尽管工艺复杂性增加。
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引用次数: 1
A voltage-regulated static keeper technique for high-performance ASICs 一种用于高性能asic的稳压静态保持技术
Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.723036
H. Kanno, T. Saeki, H. Abiko, A. Kubo, K. Tokashiki
A Voltage-Regulated Static Keeper (VRSK) technique is proposed. The VRSK can be applied to any dynamic circuit without size optimization and dissipates only one-third power of a static keeper. A 4-bit demultiplexer incorporating the VRSK can operate up to 2.0 GHz with a power consumption of only 5.8 mW.
提出了一种稳压静态保持器(VRSK)技术。VRSK可以应用于任何不需要优化尺寸的动态电路,功耗仅为静态keeper的三分之一。采用VRSK的4位解复用器可以在2.0 GHz的频率下工作,功耗仅为5.8 mW。
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引用次数: 7
Circuit techniques for high-speed and low-power multi-port SRAMs 高速低功耗多端口sram的电路技术
Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722823
M. Khellah, M. Elmasry
This paper presents a new approach based on current-mode to reduce the energy and improve the speed of write and read accesses in multi-port SRAMs. The design of a pipelined 32/spl times/64 register file that utilizes the above technique is described. Simulation results in a 0.6 /spl mu/m CMOS technology show that the register file can operate at a 500 MHz frequency using a 2.3 V supply.
本文提出了一种基于电流模式的多端口sram降低功耗、提高读写速度的新方法。本文描述了利用上述技术实现的32/spl times/64寄存器文件的流水线设计。在0.6 /spl mu/m CMOS技术下的仿真结果表明,该寄存器文件可以使用2.3 V电源在500mhz频率下工作。
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引用次数: 8
Reusable Architectures And Intellectual Property 可重用架构和知识产权
Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722989
R. Krishnamurthy, Shih-Lien Lu
The papers in this section describe reusable architectures and address some of the important issues of intellectual property. The first paper presents soft cores for well-established industrystandard microcontrollers. The authors discuss the development effort, their verification strategy and the simulation environment as well as the IP difficulties encountered. The second paper focuses on a methodology for producing process portable hard cores using a cell based array architecture. The Cell Based Array Block Expert flow is presented that can be wed to automatically port IP cores so that they are optimally implemented in a target process.
本节中的论文描述了可重用架构,并解决了一些重要的知识产权问题。第一篇论文介绍了成熟的工业标准微控制器的软核。作者讨论了开发工作,他们的验证策略和仿真环境以及IP遇到的困难。第二篇论文着重于使用基于单元的阵列架构生产过程便携式硬核的方法。提出了基于Cell的Array Block Expert流程,该流程可用于自动端口IP核,从而使其在目标进程中得到最佳实现。
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引用次数: 0
期刊
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)
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