Hardware Based RISC-V Instruction Set Randomization

Abstract

Instruction set randomization has been proposed for many years as a strategy against code injection. However, most of the methods are based entirely on software, which is vulnerable to possible threats like key leakage or bypassing attack. The translation of instructions also brings the loss of performance. Some designs randomize the instruction set based on hardware, but using weak approaches which can be easily bypassed. In this paper, we propose a hybrid instruction set randomization with both compiler support and hardware extension on a RISC-V processor. We adopt AES-128 to randomize RISC-V instruction set with little performance loss. The design has been implemented on Xilinx AV7K325 FPGA board, the results shows that RISC-V instruction set is randomized with no changes in clock frequency, 1377 LUTs increase in resources and 0.38% performance overhead.