Huabing Liao, Haikun Jia, Xiangrong Huang, Bao Shi, W. Deng, B. Chi, Zhihua Wang
{"title":"A 22.8 GHz to 32.8 GHz Compact Power Amplifier with a 15 dBm Output P1dB and 36.5% Peak PAE in 65-nm CMOS","authors":"Huabing Liao, Haikun Jia, Xiangrong Huang, Bao Shi, W. Deng, B. Chi, Zhihua Wang","doi":"10.1109/ICTA56932.2022.9963053","DOIUrl":null,"url":null,"abstract":"A CMOS broadband millimeter-wave power amplifier (PA) based on a Sandwiched Transformer (ST) output matching network is presented in this paper. The ST output matching network with a three-layer structure providing a larger coupling coefficient (k) than the traditional two-layer stack structure is proposed for PA's output matching network. The layout of the transistors is optimized to improve the PA's performance. Fabricated in 65-nm CMOS process, the PA has achieved 15 dBm OP1dBand 36.5% peak power added efficiency (PAE). The 3-dB bandwidth of the PA is from 22.8 GHz to 32.8 GHz.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICTA56932.2022.9963053","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A CMOS broadband millimeter-wave power amplifier (PA) based on a Sandwiched Transformer (ST) output matching network is presented in this paper. The ST output matching network with a three-layer structure providing a larger coupling coefficient (k) than the traditional two-layer stack structure is proposed for PA's output matching network. The layout of the transistors is optimized to improve the PA's performance. Fabricated in 65-nm CMOS process, the PA has achieved 15 dBm OP1dBand 36.5% peak power added efficiency (PAE). The 3-dB bandwidth of the PA is from 22.8 GHz to 32.8 GHz.