A 10-bit, 40 Msamples/s cascading folding and interpolating A/D converter with wide range error correction

Abstract

This paper describes a 10-bit, 10-Msamples/s CMOS folding and interpolating analog-to-digital converter (F&I ADC). A new cascading architecture is proposed to reduce the number of comparators and power consumption, and to increase input signal bandwidth. To reduce the nonlinear errors in the sample-and-holder (S/H), a charge-pump circuit is used. By using a wide range error correction scheme, the relaxed design of comparators is possible. The ADC was designed using a 0.25 /spl mu/m 1-poly 5-metal CMOS process. It consumes 62 mW at 40 Msamples/s. The INL/DNL is less than 0.5 LSB/0.4 LSB by MATLAB presimulation.