Stage-oriented, Mixed Design Methodology for Image Processing Using VHDL and Python

Abstract

The data analysis could be a very time consuming process during the hardware design on FPGA platforms. The verification process of designed modules is important at each step of a design process. In some cases standard methods for data analysis are insufficient, especially when the data representation are taken into assessment methods. In image processing systems based on FPGA there are various methods to support engineers in development of desired architecture. Some of them are based on scoping hardware signals in running device. It is also possible to scope signals in a simulation environment. In addition there are also high-level abstraction layer of data analysis methods based on Matlab, Python and similar tools. The unique image processing architecture developed by authors could not be upgraded with support of existing co-design methods. This is why stage-oriented, mixed design methodology was performed to support FPGA hardware development for faster prototyping and debugging with Vivado simulator tool and Python language. Presented approach was used to improve image processing design operating with ultra high resolution images (from 5 Mpix up to 70 Mpix).