Energy delay measures of barrel switch architectures for pre-alignment of floating point operands for addition

Abstract

Significand pre-alignment is a pre requisite for floating point additions. This paper addresses the architectural design and energy delay evaluation of a Low Power Barrel Switch for pre-alignment of floating point significands. Architectural energy delay analysis of Barrel Switch schemes suggests the suitability of transition activity scaled architectures for Low Power CMOS designs. Our energy delay estimates of operand pre-alignment Barrel Switchers for the addition of IEEE single precision floating point numbers, taking into account the architectural as well as circuit implementation issues, suggests an energy delay reduction of better than 50% for transition activity scaled architectures for coefficients of parasitic lending exceeding 10. The corresponding reduction in power consumption is more than 55%.