Since its more general introduction, adiabatic charging has been considered to have a more or less unlimited potential to reduce the power consumption of a CMOS circuit. The prediction was that when reducing operation speed the power consumption could be decreased unlimited, in extreme down to zero. However, if static losses are considered, too, a limit for the achievable minimum power consumption occurs, stating an optimum charging time with minimal power consumption, that is different from infinity, in opposition to the well known considerations used up to now. A linear network model giving the reason for such losses is introduced in this paper, together with a closed formula for the prediction of the power consumption of such a circuit. From this formula the optimum charging time and minimal power consumption can be derived, in closed form, too. Further it is shown, that for such circuits with static losses the well-known linear charging ramps do no longer form the optimal waveform for charging with low losses. These waveforms can be derived by variational calculus. By comparing the predicted energy losses to simulation results gained by using the models of a standard CMOS process, it is shown that the linear model holds in the interesting range of charging times, giving a rather precise description.
{"title":"Enhanced prediction of energy losses during adiabatic charging [CMOS circuit]","authors":"A. Schlaffer, J. Nossek","doi":"10.1109/LPE.1997.621251","DOIUrl":"https://doi.org/10.1109/LPE.1997.621251","url":null,"abstract":"Since its more general introduction, adiabatic charging has been considered to have a more or less unlimited potential to reduce the power consumption of a CMOS circuit. The prediction was that when reducing operation speed the power consumption could be decreased unlimited, in extreme down to zero. However, if static losses are considered, too, a limit for the achievable minimum power consumption occurs, stating an optimum charging time with minimal power consumption, that is different from infinity, in opposition to the well known considerations used up to now. A linear network model giving the reason for such losses is introduced in this paper, together with a closed formula for the prediction of the power consumption of such a circuit. From this formula the optimum charging time and minimal power consumption can be derived, in closed form, too. Further it is shown, that for such circuits with static losses the well-known linear charging ramps do no longer form the optimal waveform for charging with low losses. These waveforms can be derived by variational calculus. By comparing the predicted energy losses to simulation results gained by using the models of a standard CMOS process, it is shown that the linear model holds in the interesting range of charging times, giving a rather precise description.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134104952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes Booth encoded multipliers and their use in FIR filters and other DSP applications where one input is random and the other is highly correlated. Selecting the correct multiplier configuration for a given application can reduce power by more than 50% depending on the filter response. We show that applying the coefficients of an FIR filter to the Booth encoded input gives less switching activity in the multiplier than when applied to the multiplicand input. We also show that power savings are possible when using time-multiplexed multipliers to compute several filter taps. The techniques are supported with measurements from a full-custom adaptive equalizer chip for broadband communications.
{"title":"Low power multiplication for FIR filters","authors":"C. Nicol, P. Larsson","doi":"10.1145/263272.263287","DOIUrl":"https://doi.org/10.1145/263272.263287","url":null,"abstract":"This paper describes Booth encoded multipliers and their use in FIR filters and other DSP applications where one input is random and the other is highly correlated. Selecting the correct multiplier configuration for a given application can reduce power by more than 50% depending on the filter response. We show that applying the coefficients of an FIR filter to the Booth encoded input gives less switching activity in the multiplier than when applied to the multiplicand input. We also show that power savings are possible when using time-multiplexed multipliers to compute several filter taps. The techniques are supported with measurements from a full-custom adaptive equalizer chip for broadband communications.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115236813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Communications satellites use steerable antenna arrays for their communication links. These arrays need multi channel signal routing circuitry up to several tens of channels. Traditionally, this circuitry has been realized with hybrid technology. This has resulted in tens of watts of power consumption and several kilograms of payload weight. In this paper we describe monolithic integrated switch and vector modulator matrixes for signal routing and beamforming, operating in the 160 MHz IF range. These 12-16 I/O channel LSI level analogue circuits reduce the power consumption of the satellite beamforming circuitry to a few watts and weight to less than one kilogram. The power consumption per matrix node is 10-20 mW compared to the 100-500 mW consumption in the hybrid solutions.
{"title":"Analogue LSI RF switch and beamforming matrixes for communications satellites","authors":"M. Åberg, A. Leppänen, A. Rantala, J. Marjonen","doi":"10.1109/LPE.1997.621293","DOIUrl":"https://doi.org/10.1109/LPE.1997.621293","url":null,"abstract":"Communications satellites use steerable antenna arrays for their communication links. These arrays need multi channel signal routing circuitry up to several tens of channels. Traditionally, this circuitry has been realized with hybrid technology. This has resulted in tens of watts of power consumption and several kilograms of payload weight. In this paper we describe monolithic integrated switch and vector modulator matrixes for signal routing and beamforming, operating in the 160 MHz IF range. These 12-16 I/O channel LSI level analogue circuits reduce the power consumption of the satellite beamforming circuitry to a few watts and weight to less than one kilogram. The power consumption per matrix node is 10-20 mW compared to the 100-500 mW consumption in the hybrid solutions.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124272316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In CMOS technology the decomposition of the nodes of a circuit can significantly reduce the circuit power dissipation. We present a normalization algorithm which extracts the largest nodes of the given netlist. Then we examine a known node decomposition algorithm and propose a new one which is provable optimal and tractable for moderate node sizes. Reduction of the overall switching activity on standard benchmark circuits is shown for exact (ROBDD) and uncorrelated signal probabilities.
{"title":"Node normalization and decomposition in low power technology mapping","authors":"W. Nöth, Reiner Kolla","doi":"10.1145/263272.263351","DOIUrl":"https://doi.org/10.1145/263272.263351","url":null,"abstract":"In CMOS technology the decomposition of the nodes of a circuit can significantly reduce the circuit power dissipation. We present a normalization algorithm which extracts the largest nodes of the given netlist. Then we examine a known node decomposition algorithm and propose a new one which is provable optimal and tractable for moderate node sizes. Reduction of the overall switching activity on standard benchmark circuits is shown for exact (ROBDD) and uncorrelated signal probabilities.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128379506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we present a methodology and techniques for generating cycle-accurate macro-models for RT-level power analysis. The proposed macro-model predicts nor only the cycle-by-cycle power consumption of a module, but the power profile of the module over time. The proposed methodology consists of three steps: module equation form generation and variable selection, variable reduction and population stratification. First order temporal correlations and spatial correlations of up to order 3 are considered to improve the estimation accuracy. Experimental results show that, the macro-models have 15 or less variables and exhibit <5% error in average power and <15% errors in cycle-by-cycle power compared to circuit simulation results using Powermill.
{"title":"Cycle-accurate macro-models for RT-level power analysis","authors":"Qinru Qiu, Qing Wu, Massoud Pedram, Chih-Shun Ding","doi":"10.1145/263272.263305","DOIUrl":"https://doi.org/10.1145/263272.263305","url":null,"abstract":"In this paper we present a methodology and techniques for generating cycle-accurate macro-models for RT-level power analysis. The proposed macro-model predicts nor only the cycle-by-cycle power consumption of a module, but the power profile of the module over time. The proposed methodology consists of three steps: module equation form generation and variable selection, variable reduction and population stratification. First order temporal correlations and spatial correlations of up to order 3 are considered to improve the estimation accuracy. Experimental results show that, the macro-models have 15 or less variables and exhibit <5% error in average power and <15% errors in cycle-by-cycle power compared to circuit simulation results using Powermill.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123382927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
One of the most effective ways to design low power circuits is to use low power supply voltages. If the threshold voltages are also reduced, it is possible to maintain good performance at these lower voltages. This paper addresses the question of how to choose the optimum supply and threshold voltages for low power design. Other workers have also addressed this question, but have only considered nominal conditions or nominal conditions plus simplified tolerances. These prior works have used simplified models for device switching speed and power dissipation. In the present work we take more detailed account of parameter tolerances, take full account of short channel effects in the devices, and carry out full circuit simulations to obtain accurate speed and power information.
{"title":"Supply and threshold voltage optimization for low power design","authors":"D. Frank, P. Solomon, S. Reynolds, John Shin","doi":"10.1145/263272.263364","DOIUrl":"https://doi.org/10.1145/263272.263364","url":null,"abstract":"One of the most effective ways to design low power circuits is to use low power supply voltages. If the threshold voltages are also reduced, it is possible to maintain good performance at these lower voltages. This paper addresses the question of how to choose the optimum supply and threshold voltages for low power design. Other workers have also addressed this question, but have only considered nominal conditions or nominal conditions plus simplified tolerances. These prior works have used simplified models for device switching speed and power dissipation. In the present work we take more detailed account of parameter tolerances, take full account of short channel effects in the devices, and carry out full circuit simulations to obtain accurate speed and power information.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128077320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
W. Athas, N. Tzartzanis, L. Svensson, L. Peterson, Huimin Li, Xing Yu Jiang, Peiqing Wang, W.-C. Liu
We describe the design of AC-1, a low-power 16-bit microprocessor which utilizes clock-powered logic to reduce dissipation in its power-intensive sections. We present power measurements for a 0.5-/spl mu/m n-well CMOS implementation. A resonant clock driver recovers and reuses energy that would otherwise be dissipated as heat, yielding measured overall power reduction factors of four to five.
{"title":"AC-1: a clock-powered microprocessor","authors":"W. Athas, N. Tzartzanis, L. Svensson, L. Peterson, Huimin Li, Xing Yu Jiang, Peiqing Wang, W.-C. Liu","doi":"10.1145/263272.263366","DOIUrl":"https://doi.org/10.1145/263272.263366","url":null,"abstract":"We describe the design of AC-1, a low-power 16-bit microprocessor which utilizes clock-powered logic to reduce dissipation in its power-intensive sections. We present power measurements for a 0.5-/spl mu/m n-well CMOS implementation. A resonant clock driver recovers and reuses energy that would otherwise be dissipated as heat, yielding measured overall power reduction factors of four to five.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130068238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jason J. Brown, D. Chen, G. Greenwood, X. Hu, Richard W. Taylor
This paper describes how, through a combination of scheduling and buffer insertion, real-time systems may be optimized for power consumption while maintaining deadlines. Beginning with simple examples (components that have no internal pipelines and in which the only design freedoms are buffer insertion and scheduling), we illustrate the effect of adjusting the time at which data are processed on power consumption. Algorithms for optimizing the energy saving are proposed for several real-time system implementations including non-pipelined and pipelined. We also discuss extension to this preliminary work including selection of alternate processing units in order to reduce power consumption while maintaining deadlines.
{"title":"Scheduling for power reduction in a real-time system","authors":"Jason J. Brown, D. Chen, G. Greenwood, X. Hu, Richard W. Taylor","doi":"10.1145/263272.263289","DOIUrl":"https://doi.org/10.1145/263272.263289","url":null,"abstract":"This paper describes how, through a combination of scheduling and buffer insertion, real-time systems may be optimized for power consumption while maintaining deadlines. Beginning with simple examples (components that have no internal pipelines and in which the only design freedoms are buffer insertion and scheduling), we illustrate the effect of adjusting the time at which data are processed on power consumption. Algorithms for optimizing the energy saving are proposed for several real-time system implementations including non-pipelined and pipelined. We also discuss extension to this preliminary work including selection of alternate processing units in order to reduce power consumption while maintaining deadlines.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129069368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Low power signal processing systems are required for distributed network microsensor technology. Network microsensors now provide a new monitoring and control capability for civil and military applications in transportation, manufacturing, biomedical technology, environmental management, and safety and security systems. Signal processing methods for event detection have been developed with low power, parallel architectures that optimize performance for unique sensor system requirements. Implementation of parallel datapaths with shared arithmetic elements enables high throughput at low clock rate. This method has been used to implement a microsensor spectrum analyzer for a 200 sample/s measurement system. This 0.8 /spl mu/ CMOS device operates with a 1 /spl mu/A drain current at a 3 V supply bias.
{"title":"Low power signal processing architectures for network microsensors","authors":"M. Dong, K. Geoj, ey Yung, W. Kaiser","doi":"10.1145/263272.263320","DOIUrl":"https://doi.org/10.1145/263272.263320","url":null,"abstract":"Low power signal processing systems are required for distributed network microsensor technology. Network microsensors now provide a new monitoring and control capability for civil and military applications in transportation, manufacturing, biomedical technology, environmental management, and safety and security systems. Signal processing methods for event detection have been developed with low power, parallel architectures that optimize performance for unique sensor system requirements. Implementation of parallel datapaths with shared arithmetic elements enables high throughput at low clock rate. This method has been used to implement a microsensor spectrum analyzer for a 200 sample/s measurement system. This 0.8 /spl mu/ CMOS device operates with a 1 /spl mu/A drain current at a 3 V supply bias.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128797471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we propose a novel approach to synthesis for low power under tight timing constraints. Starting from a mapped netlist, we apply a powerful generalized matching algorithm based on Boolean relations that allows us to find reduced-power replacements for clusters of more than one cell. Our approach is robust and scales well with circuit size it has been tested on all largest examples of the MCNC91 benchmark suite. In average, power is reduced by more than 17% with no speed penalty compared to minimum delay implementations. Area is virtually unchanged.
{"title":"Re-mapping for low power under tight timing constraints","authors":"P. Vuillod, L. Benini, G. Micheli","doi":"10.1145/263272.263354","DOIUrl":"https://doi.org/10.1145/263272.263354","url":null,"abstract":"In this paper we propose a novel approach to synthesis for low power under tight timing constraints. Starting from a mapped netlist, we apply a powerful generalized matching algorithm based on Boolean relations that allows us to find reduced-power replacements for clusters of more than one cell. Our approach is robust and scales well with circuit size it has been tested on all largest examples of the MCNC91 benchmark suite. In average, power is reduced by more than 17% with no speed penalty compared to minimum delay implementations. Area is virtually unchanged.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124942069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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