{"title":"A current-draining folded up-conversion mixer and pre-amplifier stage in a CMOS technology for IEEE 802.11a WPAN applications","authors":"H. Ramiah, T. Zainal, A. Zulklifi","doi":"10.1109/RFIT.2005.1598902","DOIUrl":null,"url":null,"abstract":"This paper describes a 3.5-GHz up-conversion mixer core utilized in a two step transmitter architecture in compliant with IEEE 802.11a WPAN application. The design is based on current-draining folded architecture. The main advantage of the introduced mixer topology is: high linearity and moderate conversion power gain. The mixer is designed in a 0.18-/spl mu/m CMOS technology, operating from 1.8-V power supply. The integrated up-converter and preamplifier consumes 5 mA and 22 mA of current respectively from 1.8-V supply and shows 4.73-dBm OIP3 (-1.74-dBm IIP3) and -9.41-dBm P1 dB with 5.65 dBm of conversion power gain.","PeriodicalId":337918,"journal":{"name":"2005 IEEE International Wkshp on Radio-Frequency Integration Technology: Integrated Circuits for Wideband Comm & Wireless Sensor Networks","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 IEEE International Wkshp on Radio-Frequency Integration Technology: Integrated Circuits for Wideband Comm & Wireless Sensor Networks","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIT.2005.1598902","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
This paper describes a 3.5-GHz up-conversion mixer core utilized in a two step transmitter architecture in compliant with IEEE 802.11a WPAN application. The design is based on current-draining folded architecture. The main advantage of the introduced mixer topology is: high linearity and moderate conversion power gain. The mixer is designed in a 0.18-/spl mu/m CMOS technology, operating from 1.8-V power supply. The integrated up-converter and preamplifier consumes 5 mA and 22 mA of current respectively from 1.8-V supply and shows 4.73-dBm OIP3 (-1.74-dBm IIP3) and -9.41-dBm P1 dB with 5.65 dBm of conversion power gain.
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