In this paper, we correlate the two-tone test data, third order inter-modulation distortion ratio (IM3R) with the ACPR from multi-tone test for broadband signals at 1.95 GHz and 2.4 GHz. We also up-convert these broadband signals to millimeter-wave frequency to verify the correlation equation for 44-GHz power amplifiers. These measurement results show good agreement, within /spl plusmn/ 1 dB, between two-tone and multi-tone tests up to the P/sub 1 dB/ point. It is observed that, as the input power increased, the multi-tone ACPR has a similar trend as the ACPR for broadband signals, like WCDMA and 16-QAM in microwave and millimeter-wave frequency band.
{"title":"ACPR and IM3R correlation of broadband signals in microwave and millimeter wave frequencies","authors":"Wei-Chien Chen, Jeng‐Han Tsai, Shih-Yu Chen, Tian-Wei Huang","doi":"10.1109/RFIT.2005.1598897","DOIUrl":"https://doi.org/10.1109/RFIT.2005.1598897","url":null,"abstract":"In this paper, we correlate the two-tone test data, third order inter-modulation distortion ratio (IM3R) with the ACPR from multi-tone test for broadband signals at 1.95 GHz and 2.4 GHz. We also up-convert these broadband signals to millimeter-wave frequency to verify the correlation equation for 44-GHz power amplifiers. These measurement results show good agreement, within /spl plusmn/ 1 dB, between two-tone and multi-tone tests up to the P/sub 1 dB/ point. It is observed that, as the input power increased, the multi-tone ACPR has a similar trend as the ACPR for broadband signals, like WCDMA and 16-QAM in microwave and millimeter-wave frequency band.","PeriodicalId":337918,"journal":{"name":"2005 IEEE International Wkshp on Radio-Frequency Integration Technology: Integrated Circuits for Wideband Comm & Wireless Sensor Networks","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125948504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-01DOI: 10.1109/RFIT.2005.1598883
Y. Deval, O. Mazouffre, C. Majek, H. Lapuyade, T. Taris, J. Bégueret
This paper presents some new approaches for frequency generation in silicon RF integrated circuits, from either the circuit or the architecture point of view. While a phase locked loop (PLL) is classically brought into play whenever a frequency synthesis is needed, the design of key building blocks such as the RF frequency divider is a very challenge. Concerning the latter, the synchronized ring oscillator (SRO), which provides dual-modulus division at frequency above 20 GHz while consuming little power, is presented. Alternative solutions to the classical PLL, such as injection locked oscillator (ILO) and factorial delay locked loop (F-DLL) are presented as well. Advantages and drawbacks of these approaches are discussed, based upon simulation and experimental measurements.
{"title":"Disruptive design solutions for frequency generation in silicon RFIC","authors":"Y. Deval, O. Mazouffre, C. Majek, H. Lapuyade, T. Taris, J. Bégueret","doi":"10.1109/RFIT.2005.1598883","DOIUrl":"https://doi.org/10.1109/RFIT.2005.1598883","url":null,"abstract":"This paper presents some new approaches for frequency generation in silicon RF integrated circuits, from either the circuit or the architecture point of view. While a phase locked loop (PLL) is classically brought into play whenever a frequency synthesis is needed, the design of key building blocks such as the RF frequency divider is a very challenge. Concerning the latter, the synchronized ring oscillator (SRO), which provides dual-modulus division at frequency above 20 GHz while consuming little power, is presented. Alternative solutions to the classical PLL, such as injection locked oscillator (ILO) and factorial delay locked loop (F-DLL) are presented as well. Advantages and drawbacks of these approaches are discussed, based upon simulation and experimental measurements.","PeriodicalId":337918,"journal":{"name":"2005 IEEE International Wkshp on Radio-Frequency Integration Technology: Integrated Circuits for Wideband Comm & Wireless Sensor Networks","volume":"889 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114598318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-01DOI: 10.1109/RFIT.2005.1598902
H. Ramiah, T. Zainal, A. Zulklifi
This paper describes a 3.5-GHz up-conversion mixer core utilized in a two step transmitter architecture in compliant with IEEE 802.11a WPAN application. The design is based on current-draining folded architecture. The main advantage of the introduced mixer topology is: high linearity and moderate conversion power gain. The mixer is designed in a 0.18-/spl mu/m CMOS technology, operating from 1.8-V power supply. The integrated up-converter and preamplifier consumes 5 mA and 22 mA of current respectively from 1.8-V supply and shows 4.73-dBm OIP3 (-1.74-dBm IIP3) and -9.41-dBm P1 dB with 5.65 dBm of conversion power gain.
{"title":"A current-draining folded up-conversion mixer and pre-amplifier stage in a CMOS technology for IEEE 802.11a WPAN applications","authors":"H. Ramiah, T. Zainal, A. Zulklifi","doi":"10.1109/RFIT.2005.1598902","DOIUrl":"https://doi.org/10.1109/RFIT.2005.1598902","url":null,"abstract":"This paper describes a 3.5-GHz up-conversion mixer core utilized in a two step transmitter architecture in compliant with IEEE 802.11a WPAN application. The design is based on current-draining folded architecture. The main advantage of the introduced mixer topology is: high linearity and moderate conversion power gain. The mixer is designed in a 0.18-/spl mu/m CMOS technology, operating from 1.8-V power supply. The integrated up-converter and preamplifier consumes 5 mA and 22 mA of current respectively from 1.8-V supply and shows 4.73-dBm OIP3 (-1.74-dBm IIP3) and -9.41-dBm P1 dB with 5.65 dBm of conversion power gain.","PeriodicalId":337918,"journal":{"name":"2005 IEEE International Wkshp on Radio-Frequency Integration Technology: Integrated Circuits for Wideband Comm & Wireless Sensor Networks","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115123201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RFIT.2005.1598899
N. Itoh
CCV-VCO (capacitor-coupled varactor VCO) has been studied with a view to suppressing flicker noise up-conversion. The mechanisms of flicker noise up-conversion to f/sup 3/ phase noise utilize three paths; direct modulation, folding by non-linearity of oscillation, and tail current up-conversion at common node. Designed NMOS-VCO satisfied to avoid f/sup 3/ phase noise by direct modulation pass. Measured phase noise at 10 kHz offset from carrier was -74 dBc/Hz at 2.9 GHz oscillation frequency, and the corner frequency between f/sup 3/ phase noise and f/sup 2/ phase noise was approximately 20 kHz. The current consumption was 6 mA with 1.8 V. The 1 MHz FOM of VCO was 182 dB and 10 kHz FOM of VCO was 173 dB.
{"title":"A study of capacitor-coupled varactor VCO to investigate flicker noise up-conversion mechanism","authors":"N. Itoh","doi":"10.1109/RFIT.2005.1598899","DOIUrl":"https://doi.org/10.1109/RFIT.2005.1598899","url":null,"abstract":"CCV-VCO (capacitor-coupled varactor VCO) has been studied with a view to suppressing flicker noise up-conversion. The mechanisms of flicker noise up-conversion to f/sup 3/ phase noise utilize three paths; direct modulation, folding by non-linearity of oscillation, and tail current up-conversion at common node. Designed NMOS-VCO satisfied to avoid f/sup 3/ phase noise by direct modulation pass. Measured phase noise at 10 kHz offset from carrier was -74 dBc/Hz at 2.9 GHz oscillation frequency, and the corner frequency between f/sup 3/ phase noise and f/sup 2/ phase noise was approximately 20 kHz. The current consumption was 6 mA with 1.8 V. The 1 MHz FOM of VCO was 182 dB and 10 kHz FOM of VCO was 173 dB.","PeriodicalId":337918,"journal":{"name":"2005 IEEE International Wkshp on Radio-Frequency Integration Technology: Integrated Circuits for Wideband Comm & Wireless Sensor Networks","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126172700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RFIT.2005.1598908
R. Yadav, K.S. Lee, V. Bharadwaj
A band-pass filter operating in 2.40 GHz to 2.48 GHz range is designed in 0.18 /spl mu/m CMOS technology. It has tunable center frequency, Q-factor and gain. The fully integrated system-on-chip (SOC) 10th order band-pass filter is built by cascading five stages of 2nd order. The simulation of the filter on ADS software provides an insertion gain of 8 dB in the pass-band frequency from 2.40 GHz to 2.48 GHz. The attenuation in the stop-band is observed to be higher than 50 dB at 400 MHz away from pass-band edge with 15 mA current sinking from a 1.8 V supply. We present several simulation results to highlight these characteristics.
{"title":"2.40-2.48 GHz bandpass filter in 0.18 /spl mu/m CMOS","authors":"R. Yadav, K.S. Lee, V. Bharadwaj","doi":"10.1109/RFIT.2005.1598908","DOIUrl":"https://doi.org/10.1109/RFIT.2005.1598908","url":null,"abstract":"A band-pass filter operating in 2.40 GHz to 2.48 GHz range is designed in 0.18 /spl mu/m CMOS technology. It has tunable center frequency, Q-factor and gain. The fully integrated system-on-chip (SOC) 10th order band-pass filter is built by cascading five stages of 2nd order. The simulation of the filter on ADS software provides an insertion gain of 8 dB in the pass-band frequency from 2.40 GHz to 2.48 GHz. The attenuation in the stop-band is observed to be higher than 50 dB at 400 MHz away from pass-band edge with 15 mA current sinking from a 1.8 V supply. We present several simulation results to highlight these characteristics.","PeriodicalId":337918,"journal":{"name":"2005 IEEE International Wkshp on Radio-Frequency Integration Technology: Integrated Circuits for Wideband Comm & Wireless Sensor Networks","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126864414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RFIT.2005.1598865
W. Ali-Ahmad
As the era of content driven and rich multimedia mobile applications evolves, the need arises for efficient wideband cellular systems. This paper presents modern radio transceiver architectures used in 3G cellular handsets, such as EDGE, cdma2000, and WCDMA/HSDPA. This includes future /spl Sigma//spl Delta/-ADC based receiver and mostly all-digital transmitter architectures, which are being enabled by the current aggressive scaling of CMOS technology and the push toward full radio system-on-chip (SoC) integration. Furthermore, the paper focuses on discussing some key RF system design issues, and their influence on the choice of architecture used for a specific cellular radio-chipset solution.
{"title":"Radio transceiver architectures and design issues for wideband cellular systems","authors":"W. Ali-Ahmad","doi":"10.1109/RFIT.2005.1598865","DOIUrl":"https://doi.org/10.1109/RFIT.2005.1598865","url":null,"abstract":"As the era of content driven and rich multimedia mobile applications evolves, the need arises for efficient wideband cellular systems. This paper presents modern radio transceiver architectures used in 3G cellular handsets, such as EDGE, cdma2000, and WCDMA/HSDPA. This includes future /spl Sigma//spl Delta/-ADC based receiver and mostly all-digital transmitter architectures, which are being enabled by the current aggressive scaling of CMOS technology and the push toward full radio system-on-chip (SoC) integration. Furthermore, the paper focuses on discussing some key RF system design issues, and their influence on the choice of architecture used for a specific cellular radio-chipset solution.","PeriodicalId":337918,"journal":{"name":"2005 IEEE International Wkshp on Radio-Frequency Integration Technology: Integrated Circuits for Wideband Comm & Wireless Sensor Networks","volume":"1652 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129313080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RFIT.2005.1598898
C. Wang, R. Qian, Xiaowei Sun
In this paper, we produced two kinds of k band radar modules with low cost. Firstly, a 24-GHz frequency modulation continuous-wave radar sensor is presented. A resonance cavity Gunn voltage-controlled oscillator and the driver amplifier MMIC act as transmitter. In contrast, we give another framework's k band radar module, include wave guide VCO.
{"title":"Low cost k-band FMCW radar modules for automobile application","authors":"C. Wang, R. Qian, Xiaowei Sun","doi":"10.1109/RFIT.2005.1598898","DOIUrl":"https://doi.org/10.1109/RFIT.2005.1598898","url":null,"abstract":"In this paper, we produced two kinds of k band radar modules with low cost. Firstly, a 24-GHz frequency modulation continuous-wave radar sensor is presented. A resonance cavity Gunn voltage-controlled oscillator and the driver amplifier MMIC act as transmitter. In contrast, we give another framework's k band radar module, include wave guide VCO.","PeriodicalId":337918,"journal":{"name":"2005 IEEE International Wkshp on Radio-Frequency Integration Technology: Integrated Circuits for Wideband Comm & Wireless Sensor Networks","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114730046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RFIT.2005.1598878
J. Cheah
The cost difference between wireless systems made of discrete components and system-on-chip solutions made using bulk CMOS is diminishing. Assuming that engineering design domain knowledge is already in place, the processes of designing both discrete and SOC wireless communications systems are converging in terms of time and economics. The time has come to consider the option of replacing traditional PCB and discrete devices with fully-integrated silicon designs. This paper discusses the rationale behind this paradigm shift.
{"title":"A paradigm shift in mixed-signal bulk CMOS product-on-chip design","authors":"J. Cheah","doi":"10.1109/RFIT.2005.1598878","DOIUrl":"https://doi.org/10.1109/RFIT.2005.1598878","url":null,"abstract":"The cost difference between wireless systems made of discrete components and system-on-chip solutions made using bulk CMOS is diminishing. Assuming that engineering design domain knowledge is already in place, the processes of designing both discrete and SOC wireless communications systems are converging in terms of time and economics. The time has come to consider the option of replacing traditional PCB and discrete devices with fully-integrated silicon designs. This paper discusses the rationale behind this paradigm shift.","PeriodicalId":337918,"journal":{"name":"2005 IEEE International Wkshp on Radio-Frequency Integration Technology: Integrated Circuits for Wideband Comm & Wireless Sensor Networks","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131997657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RFIT.2005.1598871
W. Heinrich
Emerging markets for mm-wave wireless and sensor systems as well as high bit-rate components demand for cost-effective packaging solutions. Flip-chip is one of the most promising approaches in this regard combining high-volume potential with excellent high-frequency performance. The talk presents the different flip-chip concepts in use, focusing on the microwave characteristics and approaching the subject from the designer's point of view. Basic electromagnetic properties of the interconnects as well as consequences for chip and package design are discussed. As carrier substrates, conventional ceramics, thin-film, and LTCC-multilayer approaches are covered. Experimental results for various applications document feasibility and capabilities in the frequency range up to 100 GHz.
{"title":"Flip-chip for millimeter-wave and broadband packaging","authors":"W. Heinrich","doi":"10.1109/RFIT.2005.1598871","DOIUrl":"https://doi.org/10.1109/RFIT.2005.1598871","url":null,"abstract":"Emerging markets for mm-wave wireless and sensor systems as well as high bit-rate components demand for cost-effective packaging solutions. Flip-chip is one of the most promising approaches in this regard combining high-volume potential with excellent high-frequency performance. The talk presents the different flip-chip concepts in use, focusing on the microwave characteristics and approaching the subject from the designer's point of view. Basic electromagnetic properties of the interconnects as well as consequences for chip and package design are discussed. As carrier substrates, conventional ceramics, thin-film, and LTCC-multilayer approaches are covered. Experimental results for various applications document feasibility and capabilities in the frequency range up to 100 GHz.","PeriodicalId":337918,"journal":{"name":"2005 IEEE International Wkshp on Radio-Frequency Integration Technology: Integrated Circuits for Wideband Comm & Wireless Sensor Networks","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131089935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RFIT.2005.1598877
C. Ta, C. Yong, W. Yeoh
This paper presents a low-power and small-size variable gain amplifier (VGA) which consumes only 2.7 mW and occupies only 243 /spl mu/m /spl times/ 264 /spl mu/m (/spl sim/0.064 mm/sup 2/) in 0.18-/spl mu/m CMOS technology. The VGA is fully differential with differential output swing of 1-V/sub pp/. The gain (in dB) of the VGA can be varied linearly from -3 dB to 57 dB with respect to a control voltage from 0.2 V to 0.9 V. The VGA has a 3-dB bandwidth of more than 100 MHz for all levels of gain. The VGA also has two DC offset cancellation loops to avoid the amplification of DC offset. The output DC offset of the VGA is less than 20 mV even if an input DC offset of 40 mV is introduced to the VGA. Low power consumption is obtained owing to high transition frequency of the transistors in 0.18-/spl mu/m CMOS technology. Small area is achieved by minimizing the passive component's values and areas.
{"title":"A 2.7 mW, 0.064 mm/sup 2/ linear-in-dB VGA with 60 dB tuning range, 100 MHz bandwidth, and two DC offset cancellation loops","authors":"C. Ta, C. Yong, W. Yeoh","doi":"10.1109/RFIT.2005.1598877","DOIUrl":"https://doi.org/10.1109/RFIT.2005.1598877","url":null,"abstract":"This paper presents a low-power and small-size variable gain amplifier (VGA) which consumes only 2.7 mW and occupies only 243 /spl mu/m /spl times/ 264 /spl mu/m (/spl sim/0.064 mm/sup 2/) in 0.18-/spl mu/m CMOS technology. The VGA is fully differential with differential output swing of 1-V/sub pp/. The gain (in dB) of the VGA can be varied linearly from -3 dB to 57 dB with respect to a control voltage from 0.2 V to 0.9 V. The VGA has a 3-dB bandwidth of more than 100 MHz for all levels of gain. The VGA also has two DC offset cancellation loops to avoid the amplification of DC offset. The output DC offset of the VGA is less than 20 mV even if an input DC offset of 40 mV is introduced to the VGA. Low power consumption is obtained owing to high transition frequency of the transistors in 0.18-/spl mu/m CMOS technology. Small area is achieved by minimizing the passive component's values and areas.","PeriodicalId":337918,"journal":{"name":"2005 IEEE International Wkshp on Radio-Frequency Integration Technology: Integrated Circuits for Wideband Comm & Wireless Sensor Networks","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133503431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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