A novel Dynamic Partial Reconfiguration design for automatic white balance

Abstract

Auto white balancing is the process of keeping the color of objects constant automatically under different illumination conditions by calculating a number of parameters from the image data. These parameters are used to change the image pixel values to keep the color constant. This paper discusses the Lam's auto white balance algorithm and presents a novel, high-performance and cost-effective implementation of the algorithm in Field Programmable Gate Arrays (FPGAs) using Dynamic Partial Reconfiguration (DPR) feature to exploit the FPGA resources over time and space. The paper shows that the system with DPR saves 25% of the resources compared to the static design. Moreover, the power consumption is reduced by 13%. On the other hand, the performance of the DPR design is compared to the static design through two different techniques. The first technique targets low resources utilisation and the second targets higher throughput rate while the resource utilisation is in the range of the static design. The results show that the performance of the second technique is better than the static design. The architectures are designed to process images of size 1920x1080 within 16.78ms, 15.06ms and 11ms for first DPR technique, static design and second DPR technique respectively. Our proposed hardware architecture is shown to outperform previous hardware implementations of the algorithm and is being capable of processing up to 550 MPixels/s.