Pub Date : 2014-07-14DOI: 10.1109/AHS.2014.6880175
Pedro Rodrigues, André Oliveira, G. Oddi, F. Liberati, Francisco Alvarez, R. Cabás, T. Vladimirova, X. Zhai, Hongyuan Jing, M. Crosnier
Wireless Sensor Networks (WSNs) are made of a usually large number of nodes deployed over an area of interest in order to monitor specific phenomena. WSNs constitute a promising technology for planetary exploration, since they can be deployed in order to monitor the environmental conditions on a planet's surface, also in view of possible manned missions. This paper deals with the design of node and network architectures in a WSN targeted for planetary exploration, with a particular focus on the challenges, the driving principles and the design solutions adopted at WSN node and network level. Also, the paper introduces the basic architecture supporting data fusion at node and network level, which plays a fundamental role in order to increase overall WSN performances.
{"title":"Space Wireless Sensor Networks for planetary exploration: Node and network architectures","authors":"Pedro Rodrigues, André Oliveira, G. Oddi, F. Liberati, Francisco Alvarez, R. Cabás, T. Vladimirova, X. Zhai, Hongyuan Jing, M. Crosnier","doi":"10.1109/AHS.2014.6880175","DOIUrl":"https://doi.org/10.1109/AHS.2014.6880175","url":null,"abstract":"Wireless Sensor Networks (WSNs) are made of a usually large number of nodes deployed over an area of interest in order to monitor specific phenomena. WSNs constitute a promising technology for planetary exploration, since they can be deployed in order to monitor the environmental conditions on a planet's surface, also in view of possible manned missions. This paper deals with the design of node and network architectures in a WSN targeted for planetary exploration, with a particular focus on the challenges, the driving principles and the design solutions adopted at WSN node and network level. Also, the paper introduces the basic architecture supporting data fusion at node and network level, which plays a fundamental role in order to increase overall WSN performances.","PeriodicalId":428581,"journal":{"name":"2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117100594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-07-14DOI: 10.1109/AHS.2014.6880163
Byron Navas, Johnny Öberg, I. Sander
Advancing integration reaching atomic-scales makes components highly defective and unstable during lifetime. This demands paradigm shifts in electronic systems design. FPGAs are particularly sensitive to cosmic and other kinds of radiations that produce single-event-upsets (SEU) in configuration and internal memories. Typical fault-tolerance (FT) techniques combine triple-modular-redundancy (TMR) schemes with run-time-reconfiguration (RTR). However, even the most successful approaches disregard the low suitability of fine-grain redundancy in nano-scale design, poor scalability and programmability of application specific architectures, small performance-consumption ratio of board-level designs, or scarce optimization capability of rigid redundancy structures. In that context, we introduce an innovative solution that exploits the flexibility, reusability, and scalability of a modular RTR SoC approach and reuse existing RTR IP-cores in order to assemble different TMR schemes during run-time. Thus, the system can adaptively trigger the adequate self-healing strategy according to execution environment metrics and user-defined goals. Specifically the paper presents: (a) the upset-fault-observer (UFO), an innovative run-time self-test and recovery strategy that delivers FT on request over several function cores but saves the redundancy scalability cost by running periodic reconfigurable TMR scan-cycles, (b) run-time reconfigurable TMR schemes and self-repair mechanisms, and (c) an adaptive software organization model to manage the proposed FT strategies.
{"title":"The upset-fault-observer: A concept for self-healing adaptive fault tolerance","authors":"Byron Navas, Johnny Öberg, I. Sander","doi":"10.1109/AHS.2014.6880163","DOIUrl":"https://doi.org/10.1109/AHS.2014.6880163","url":null,"abstract":"Advancing integration reaching atomic-scales makes components highly defective and unstable during lifetime. This demands paradigm shifts in electronic systems design. FPGAs are particularly sensitive to cosmic and other kinds of radiations that produce single-event-upsets (SEU) in configuration and internal memories. Typical fault-tolerance (FT) techniques combine triple-modular-redundancy (TMR) schemes with run-time-reconfiguration (RTR). However, even the most successful approaches disregard the low suitability of fine-grain redundancy in nano-scale design, poor scalability and programmability of application specific architectures, small performance-consumption ratio of board-level designs, or scarce optimization capability of rigid redundancy structures. In that context, we introduce an innovative solution that exploits the flexibility, reusability, and scalability of a modular RTR SoC approach and reuse existing RTR IP-cores in order to assemble different TMR schemes during run-time. Thus, the system can adaptively trigger the adequate self-healing strategy according to execution environment metrics and user-defined goals. Specifically the paper presents: (a) the upset-fault-observer (UFO), an innovative run-time self-test and recovery strategy that delivers FT on request over several function cores but saves the redundancy scalability cost by running periodic reconfigurable TMR scan-cycles, (b) run-time reconfigurable TMR schemes and self-repair mechanisms, and (c) an adaptive software organization model to manage the proposed FT strategies.","PeriodicalId":428581,"journal":{"name":"2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125750424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-07-14DOI: 10.1109/AHS.2014.6880160
David M. R. Lawson, James Alfred Walker, M. Trefzer, S. Bale, A. Tyrrell
This paper presents the concept of hierarchical reconfiguration strategies that can be applied to a circuit on a reconfigurable architecture to change the implementation without changing the functionality, and their use to overcome faults in a source agnostic way. The Programmable Analogue and Digital Array (PAnDA) is a novel FPGA-like reconfigurable architecture, with configuration options below the digital layer. The PAnDA architecture includes symmetry and homogeneity at multiple levels of the configuration hierarchy. These properties could be exploited to take advantage of redundant resources in the event of a fault. To demonstrate this, faults are injected, repeatedly and at random, to a configured logic function until functionality breaks. Reconfiguration strategies are then applied at random in repeated steps to the faulty circuit until functionality is restored (or a set number of steps have been taken). An experiment is conducted to investigate whether controlling the probability of picking a particular strategy at each step can improve the average efficiency of fault recovery for a given function. It is found that the average number of steps required to fix a fault can be reduced while it is possible to increase the average number of circuits that can be fixed.
{"title":"A hierarchical fault tolerant system on the PAnDA device with low disruption","authors":"David M. R. Lawson, James Alfred Walker, M. Trefzer, S. Bale, A. Tyrrell","doi":"10.1109/AHS.2014.6880160","DOIUrl":"https://doi.org/10.1109/AHS.2014.6880160","url":null,"abstract":"This paper presents the concept of hierarchical reconfiguration strategies that can be applied to a circuit on a reconfigurable architecture to change the implementation without changing the functionality, and their use to overcome faults in a source agnostic way. The Programmable Analogue and Digital Array (PAnDA) is a novel FPGA-like reconfigurable architecture, with configuration options below the digital layer. The PAnDA architecture includes symmetry and homogeneity at multiple levels of the configuration hierarchy. These properties could be exploited to take advantage of redundant resources in the event of a fault. To demonstrate this, faults are injected, repeatedly and at random, to a configured logic function until functionality breaks. Reconfiguration strategies are then applied at random in repeated steps to the faulty circuit until functionality is restored (or a set number of steps have been taken). An experiment is conducted to investigate whether controlling the probability of picking a particular strategy at each step can improve the average efficiency of fault recovery for a given function. It is found that the average number of steps required to fix a fault can be reduced while it is possible to increase the average number of circuits that can be fixed.","PeriodicalId":428581,"journal":{"name":"2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116002378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-07-14DOI: 10.1109/AHS.2014.6880179
Rui Yao, Kun He, Yanmei Sun, You-ren Wang
A learning engine for cognitive radio based on the immune principle is proposed, in which the monkey-king's marrying mechanism is introduced to improve the learning efficiency, and the dissimilar matrix as well as fuzzy selection are utilized to simplify computation and to accelerate the learning speed. The framework of the proposed learning engine has been given. The learning engine has been implemented in MATLAB, and a test bed that simulates the wireless communication system has been developed using SIMULINK based on the 802.11a model. Simulations have been done on the parameters adjustment of multi-carrier system to perform multi-objective optimization. Experimental results indicate the superior performance of our learning engine over the genetic algorithm-based one. Furthermore, the learning engine also has the potential of decision-making because it has combined the theories of knowledge base and case-based decision-making owing to the recollection of immune system.
{"title":"Learning engine for cognitive radio based on the immune principle","authors":"Rui Yao, Kun He, Yanmei Sun, You-ren Wang","doi":"10.1109/AHS.2014.6880179","DOIUrl":"https://doi.org/10.1109/AHS.2014.6880179","url":null,"abstract":"A learning engine for cognitive radio based on the immune principle is proposed, in which the monkey-king's marrying mechanism is introduced to improve the learning efficiency, and the dissimilar matrix as well as fuzzy selection are utilized to simplify computation and to accelerate the learning speed. The framework of the proposed learning engine has been given. The learning engine has been implemented in MATLAB, and a test bed that simulates the wireless communication system has been developed using SIMULINK based on the 802.11a model. Simulations have been done on the parameters adjustment of multi-carrier system to perform multi-objective optimization. Experimental results indicate the superior performance of our learning engine over the genetic algorithm-based one. Furthermore, the learning engine also has the potential of decision-making because it has combined the theories of knowledge base and case-based decision-making owing to the recollection of immune system.","PeriodicalId":428581,"journal":{"name":"2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116419665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-07-14DOI: 10.1109/AHS.2014.6880188
D. Keymeulen, N. Aranki, A. Bakhshi, H. Luong, C. Sarture, D. Dolman
Efficient on-board lossless hyperspectral data compression reduces data volume in order to meet NASA and DoD limited downlink capabilities. The technique also improves signature extraction, object recognition and feature classification capabilities by providing exact reconstructed data on constrained downlink resources. At JPL a novel, adaptive and predictive technique for lossless compression of hyperspectral data was recently developed. This technique uses an adaptive filtering method and achieves a combination of low complexity and compression effectiveness that far exceeds state-of-the-art techniques currently in use. The JPL-developed `Fast Lossless' algorithm requires no training data or other specific information about the nature of the spectral bands for a fixed instrument dynamic range. It is of low computational complexity and thus well-suited for implementation in hardware. A prototype of the compressor (and decompressor) of the algorithm is available in software, but this implementation may not meet speed and real-time requirements of some space applications. This paper describes a hardware implementation of the `Modified Fast Lossless' compression algorithm for push broom instruments on a Field Programmable Gate Array (FPGA). The FPGA implementation has been integrated into the Next Generation Data Capture System (NGDCS) avionics system for the Airborne Visible/ Infrared Imaging Spectrometer Next Generation (AVIRISng). The NGDCS includes two airborne hardware platforms which were flown on a Twin Otter aircraft: a National Instrument PXI and the Alpha Data Systems. The FPGA implementation targets the current state-of-the-art FPGAs (Xilinx Virtex V and VI families) and compresses one sample every clock cycle to provide a fast and practical real-time solution for Space applications.
{"title":"Airborne demonstration of FPGA implementation of Fast Lossless hyperspectral data compression system","authors":"D. Keymeulen, N. Aranki, A. Bakhshi, H. Luong, C. Sarture, D. Dolman","doi":"10.1109/AHS.2014.6880188","DOIUrl":"https://doi.org/10.1109/AHS.2014.6880188","url":null,"abstract":"Efficient on-board lossless hyperspectral data compression reduces data volume in order to meet NASA and DoD limited downlink capabilities. The technique also improves signature extraction, object recognition and feature classification capabilities by providing exact reconstructed data on constrained downlink resources. At JPL a novel, adaptive and predictive technique for lossless compression of hyperspectral data was recently developed. This technique uses an adaptive filtering method and achieves a combination of low complexity and compression effectiveness that far exceeds state-of-the-art techniques currently in use. The JPL-developed `Fast Lossless' algorithm requires no training data or other specific information about the nature of the spectral bands for a fixed instrument dynamic range. It is of low computational complexity and thus well-suited for implementation in hardware. A prototype of the compressor (and decompressor) of the algorithm is available in software, but this implementation may not meet speed and real-time requirements of some space applications. This paper describes a hardware implementation of the `Modified Fast Lossless' compression algorithm for push broom instruments on a Field Programmable Gate Array (FPGA). The FPGA implementation has been integrated into the Next Generation Data Capture System (NGDCS) avionics system for the Airborne Visible/ Infrared Imaging Spectrometer Next Generation (AVIRISng). The NGDCS includes two airborne hardware platforms which were flown on a Twin Otter aircraft: a National Instrument PXI and the Alpha Data Systems. The FPGA implementation targets the current state-of-the-art FPGAs (Xilinx Virtex V and VI families) and compresses one sample every clock cycle to provide a fast and practical real-time solution for Space applications.","PeriodicalId":428581,"journal":{"name":"2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128180723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-07-14DOI: 10.1109/AHS.2014.6880169
Hongyuan Jing, T. Vladimirova
Close range optical images are considered as useful inputs to current object detection systems. By using image fusion techniques, the object detection system can reduce the redundant information from the input image and improve its understanding about the close range environment. Recently multi-focus image fusion has been applied to adaptive landmine detection systems. This paper proposes a new PCA based adaptive image fusion algorithm to fuse multi-focus images with the same visual angle but different focus. The core of the algorithm is a new technique for comparing each pixel's covariance matrix with the average covariance matrix. The test results show that the proposed algorithm outperforms state-of-the-art multi-focus image fusion algorithms. In addition, the proposed algorithm features lower implementation costs, which is suitable for the embedded systems.
{"title":"Novel PCA based pixel-level multi-focus image fusion algorithm","authors":"Hongyuan Jing, T. Vladimirova","doi":"10.1109/AHS.2014.6880169","DOIUrl":"https://doi.org/10.1109/AHS.2014.6880169","url":null,"abstract":"Close range optical images are considered as useful inputs to current object detection systems. By using image fusion techniques, the object detection system can reduce the redundant information from the input image and improve its understanding about the close range environment. Recently multi-focus image fusion has been applied to adaptive landmine detection systems. This paper proposes a new PCA based adaptive image fusion algorithm to fuse multi-focus images with the same visual angle but different focus. The core of the algorithm is a new technique for comparing each pixel's covariance matrix with the average covariance matrix. The test results show that the proposed algorithm outperforms state-of-the-art multi-focus image fusion algorithms. In addition, the proposed algorithm features lower implementation costs, which is suitable for the embedded systems.","PeriodicalId":428581,"journal":{"name":"2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128909942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-07-14DOI: 10.1109/AHS.2014.6880165
Giuseppe Airò Farulla, Marco Indaco, P. Prinetto, Daniele Rolfo, Pascal Trotta
If a camera moves while taking a picture, motion blur is induced. There exist mechanical techniques to prevent this effect to occur, but they are cumbersome and expensive. Considering for example an Unmanned Aerial Vehicle (UAV) engaged in a save and rescue mission, where recording frames of scene to identify people and animals to rescue is required. In such cases, weight of equipments is of absolute importance, and no extra hardware can be used. In such case, vibrations are unavoidably transmitted to the camera, and recorded frames are affected by blur. It is then necessary to deblur in real-time every frame to allow post-processing algorithms to extract the largest possible amount of information from them. For more than 40 years, numerous researchers have developed theories and algorithms for this purpose, which work quite well but very often require multiple different versions of the input image, huge amount of computational resources, large execution times or intensive parameters tuning.
{"title":"ABLUR: An FPGA-based adaptive deblurring core for real-time applications","authors":"Giuseppe Airò Farulla, Marco Indaco, P. Prinetto, Daniele Rolfo, Pascal Trotta","doi":"10.1109/AHS.2014.6880165","DOIUrl":"https://doi.org/10.1109/AHS.2014.6880165","url":null,"abstract":"If a camera moves while taking a picture, motion blur is induced. There exist mechanical techniques to prevent this effect to occur, but they are cumbersome and expensive. Considering for example an Unmanned Aerial Vehicle (UAV) engaged in a save and rescue mission, where recording frames of scene to identify people and animals to rescue is required. In such cases, weight of equipments is of absolute importance, and no extra hardware can be used. In such case, vibrations are unavoidably transmitted to the camera, and recorded frames are affected by blur. It is then necessary to deblur in real-time every frame to allow post-processing algorithms to extract the largest possible amount of information from them. For more than 40 years, numerous researchers have developed theories and algorithms for this purpose, which work quite well but very often require multiple different versions of the input image, huge amount of computational resources, large execution times or intensive parameters tuning.","PeriodicalId":428581,"journal":{"name":"2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122277412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-07-14DOI: 10.1109/AHS.2014.6880158
J. Núñez-Yáñez, A. Beldachi
This paper investigates how a wide dynamic range of performance and power levels can be obtained in commercially available state-of-the-art hybrid FPGAs that include ARM embedded processors and independent power domains. Adaptive voltage and frequency scaling obtained with embedded in-situ detectors in a closed loop configuration is employed to scale performance and power in the FPGA fabric under processor control. The initial results are based on a high-performance motion estimation processor mapped to the FPGA fabric and show that it is possible to obtain energy savings higher than 60% or alternatively double performance at nominal energy. The available voltage and frequency margins in the device create a large number of performance and energy states with scaling possible at run-time with low overheads.
{"title":"Run-time power and performance scaling with CPU-FPGA hybrids","authors":"J. Núñez-Yáñez, A. Beldachi","doi":"10.1109/AHS.2014.6880158","DOIUrl":"https://doi.org/10.1109/AHS.2014.6880158","url":null,"abstract":"This paper investigates how a wide dynamic range of performance and power levels can be obtained in commercially available state-of-the-art hybrid FPGAs that include ARM embedded processors and independent power domains. Adaptive voltage and frequency scaling obtained with embedded in-situ detectors in a closed loop configuration is employed to scale performance and power in the FPGA fabric under processor control. The initial results are based on a high-performance motion estimation processor mapped to the FPGA fabric and show that it is possible to obtain energy savings higher than 60% or alternatively double performance at nominal energy. The available voltage and frequency margins in the device create a large number of performance and energy states with scaling possible at run-time with low overheads.","PeriodicalId":428581,"journal":{"name":"2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124360396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-07-14DOI: 10.1109/AHS.2014.6880164
N. Ramakrishnan, Meiqing Wu, S. Lam, T. Srikanthan
Widely-used corner detectors such as Shi-Tomasi and Harris necessitate the selection of a threshold parameter manually in order to identify good quality corners. The recent attempts based on trial-and-error methods for threshold setting are time-consuming, making them unsuitable for low-cost and embedded video processing applications. In this paper we propose a novel automated thresholding technique for Shi-Tomasi and Harris corner detectors based on an iterative pruning strategy. The proposed pruning strategy involves the rapid extraction of potential corner regions and their evaluation for detecting corners. This pruning strategy is applied iteratively until the required number of corners is identified without necessitating the selection of the threshold parameter. As the complex corner measure computations of the Shi-Tomasi and Harris detectors are only applied to very small regions selected by the proposed pruning method, significant savings in computation is also achieved. In addition, the pruning strategy is computationally simpler, making it suitable for deployment in low cost and embedded applications. Our evaluations on the NiOS-II embedded platform show that the proposed automated thresholding technique is able to achieve an average speedup of 67% in Shi-Tomasi and 51% in Harris, with almost no loss in accuracy. The proposed method to identify corners without the manual selection of a threshold parameter makes it ideal for corner detection on a wide range of imagery where the quantity and quality of corners is not known a priori such as in video processing applications.
{"title":"Automated thresholding for low-complexity corner detection","authors":"N. Ramakrishnan, Meiqing Wu, S. Lam, T. Srikanthan","doi":"10.1109/AHS.2014.6880164","DOIUrl":"https://doi.org/10.1109/AHS.2014.6880164","url":null,"abstract":"Widely-used corner detectors such as Shi-Tomasi and Harris necessitate the selection of a threshold parameter manually in order to identify good quality corners. The recent attempts based on trial-and-error methods for threshold setting are time-consuming, making them unsuitable for low-cost and embedded video processing applications. In this paper we propose a novel automated thresholding technique for Shi-Tomasi and Harris corner detectors based on an iterative pruning strategy. The proposed pruning strategy involves the rapid extraction of potential corner regions and their evaluation for detecting corners. This pruning strategy is applied iteratively until the required number of corners is identified without necessitating the selection of the threshold parameter. As the complex corner measure computations of the Shi-Tomasi and Harris detectors are only applied to very small regions selected by the proposed pruning method, significant savings in computation is also achieved. In addition, the pruning strategy is computationally simpler, making it suitable for deployment in low cost and embedded applications. Our evaluations on the NiOS-II embedded platform show that the proposed automated thresholding technique is able to achieve an average speedup of 67% in Shi-Tomasi and 51% in Harris, with almost no loss in accuracy. The proposed method to identify corners without the manual selection of a threshold parameter makes it ideal for corner detection on a wide range of imagery where the quantity and quality of corners is not known a priori such as in video processing applications.","PeriodicalId":428581,"journal":{"name":"2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134085408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-07-14DOI: 10.1109/AHS.2014.6880162
Ali Ebrahim, T. Arslan, X. Iturbe
In fault-tolerant FPGA systems, the internal reconfiguration capabilities supported in modern FPGAs is commonly utilized for enhanced fault mitigation. In such systems, faults in the internal configuration controller can degrade the fault-tolerance of the system and in extreme cases can lead to additional faults injected into the system. In this paper we present different methods for enhancing the reliability of internal configuration controllers in FPGAs. We demonstrate the design of a custom ICAP controller for Xilinx Virtex FPGAs and compare the reliability and area overhead for Triple Modular Redundancy (TMR), Dual Modular Redundancy (DMR) and Cyclic Redundancy Check (CRC) design schemes. We also evaluate the effectiveness of internal readback and external configuration memory scrubbing and show how a combination of the two methods can reduce the number of single points of failure in the system.
{"title":"On enhancing the reliability of internal configuration controllers in FPGAs","authors":"Ali Ebrahim, T. Arslan, X. Iturbe","doi":"10.1109/AHS.2014.6880162","DOIUrl":"https://doi.org/10.1109/AHS.2014.6880162","url":null,"abstract":"In fault-tolerant FPGA systems, the internal reconfiguration capabilities supported in modern FPGAs is commonly utilized for enhanced fault mitigation. In such systems, faults in the internal configuration controller can degrade the fault-tolerance of the system and in extreme cases can lead to additional faults injected into the system. In this paper we present different methods for enhancing the reliability of internal configuration controllers in FPGAs. We demonstrate the design of a custom ICAP controller for Xilinx Virtex FPGAs and compare the reliability and area overhead for Triple Modular Redundancy (TMR), Dual Modular Redundancy (DMR) and Cyclic Redundancy Check (CRC) design schemes. We also evaluate the effectiveness of internal readback and external configuration memory scrubbing and show how a combination of the two methods can reduce the number of single points of failure in the system.","PeriodicalId":428581,"journal":{"name":"2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114795713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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