{"title":"Power scan: DFT for power switches in VLSI designs","authors":"B. Bai, C. Li, A. Kifli, E. Tsai, Kun-Cheng Wu","doi":"10.1109/TEST.2009.5355631","DOIUrl":null,"url":null,"abstract":"This poster presents Power Scan, a design-for-testability for power switches in VLSI designs. It measures IR drop in function mode and detects leakage current in sleep mode. Power Scan reduces the test cost at the price of small area overhead.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Test Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.2009.5355631","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This poster presents Power Scan, a design-for-testability for power switches in VLSI designs. It measures IR drop in function mode and detects leakage current in sleep mode. Power Scan reduces the test cost at the price of small area overhead.
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