Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355722
Brendan Mullane, Vincent O’Brien, Ciaran MacNamee, Thomas Fleischmann
An on-chip BIST solution performing accurate ADC measurements is presented. The platform enables linear and dynamic testing to occur in parallel, significantly lowering test time and cost. On-chip hardware resources are optimized for ADC test application.
{"title":"A2DTest: A complete integrated solution for on-chip ADC self-test and analysis","authors":"Brendan Mullane, Vincent O’Brien, Ciaran MacNamee, Thomas Fleischmann","doi":"10.1109/TEST.2009.5355722","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355722","url":null,"abstract":"An on-chip BIST solution performing accurate ADC measurements is presented. The platform enables linear and dynamic testing to occur in parallel, significantly lowering test time and cost. On-chip hardware resources are optimized for ADC test application.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127495976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355768
Takahiro J. Yamaguchi, K. Ichiyama, X. Hou, M. Ishida
A new method for identifying a deterministic jitter (DJ) model in a total jitter (TJ) distribution is introduced in this paper. The new method is based on the characteristic function and identifies the DJ model from the given TJ PDF contaminated by an unknown DJ PDF. Benchmark testing using sinusoidal jitter provides validation of the new method for high-performance identification of the DJ model. Experiments on a variety of TJ PDFs also validate the very low false alarm probability of the new method.
{"title":"A robust method for identifying a deterministic jitter model in a total jitter distribution","authors":"Takahiro J. Yamaguchi, K. Ichiyama, X. Hou, M. Ishida","doi":"10.1109/TEST.2009.5355768","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355768","url":null,"abstract":"A new method for identifying a deterministic jitter (DJ) model in a total jitter (TJ) distribution is introduced in this paper. The new method is based on the characteristic function and identifies the DJ model from the given TJ PDF contaminated by an unknown DJ PDF. Benchmark testing using sinusoidal jitter provides validation of the new method for high-performance identification of the DJ model. Experiments on a variety of TJ PDFs also validate the very low false alarm probability of the new method.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125543309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355542
Rex Petersen, P. Pant, Pablo Lopez, Aaron Barton, Jim Ignowski, Doug Josephson
Voltage transients from circuit activity impact operation, testing and debug of complex designs. This paper describes a system which enables voltage transient detection and a capability to induce voltage transients in a controlled manner. Usage models and silicon results are described, along with limitations and future options for improvements.
{"title":"Voltage transient detection and induction for debug and test","authors":"Rex Petersen, P. Pant, Pablo Lopez, Aaron Barton, Jim Ignowski, Doug Josephson","doi":"10.1109/TEST.2009.5355542","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355542","url":null,"abstract":"Voltage transients from circuit activity impact operation, testing and debug of complex designs. This paper describes a system which enables voltage transient detection and a capability to induce voltage transients in a controlled manner. Usage models and silicon results are described, along with limitations and future options for improvements.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122326504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Considering the physical layout, a comprehensive TCAM test scheme divides TCAM test into test for TCAM core and test for peripheral circuit. Besides, it schedules the existing test algorithms to develop an optimized test algorithm.
{"title":"A comprehensive TCAM test scheme: An optimized test algorithm considering physical layout and combining scan test with at-speed BIST design","authors":"Hsiang-Huang Wu, Jih-Nung Lee, Ming-Cheng Chiang, Po-Wei Liu, Chi-Feng Wu","doi":"10.1109/TEST.2009.5355536","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355536","url":null,"abstract":"Considering the physical layout, a comprehensive TCAM test scheme divides TCAM test into test for TCAM core and test for peripheral circuit. Besides, it schedules the existing test algorithms to develop an optimized test algorithm.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122164996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355625
E. Yilmaz, A. Nassery, S. Ozev, E. Acar
In this paper, we present a technique to enable accurate built-in measurement of EVM for OFDM transceivers. This measurement technique only relies on the decoded bit pattern, and does not require any additional test equipment. In order to accurately predict EVM without using analog signal analysis, we intentionally code more symbols into the bit pattern in test mode, which enables the decoding of IQ signals in finer granularity. We present an innovative DFT technique to measure EVM on-chip with very little overhead. We also provide an analytical framework to determine how the DFT technique needs to be implemented. Experimental results using MATLAB simulations and hardware measurements confirm the accuracy of the proposed technique.
{"title":"Built-in EVM measurement for OFDM transceivers using all-digital DFT","authors":"E. Yilmaz, A. Nassery, S. Ozev, E. Acar","doi":"10.1109/TEST.2009.5355625","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355625","url":null,"abstract":"In this paper, we present a technique to enable accurate built-in measurement of EVM for OFDM transceivers. This measurement technique only relies on the decoded bit pattern, and does not require any additional test equipment. In order to accurately predict EVM without using analog signal analysis, we intentionally code more symbols into the bit pattern in test mode, which enables the decoding of IQ signals in finer granularity. We present an innovative DFT technique to measure EVM on-chip with very little overhead. We also provide an analytical framework to determine how the DFT technique needs to be implemented. Experimental results using MATLAB simulations and hardware measurements confirm the accuracy of the proposed technique.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132012002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355834
M. Kamm
This poster will provide a high-level description of Cisco's manufacturing process including how, where and in what form data is collected at various test steps. Trade offs are described to optimize test time and diagnostics for any failing parts in order to provide actionable data for failure analysis. The principal goal of the poster is to raise awareness regarding base component requirements for embedded instrumentation to allow for optimal diagnostic results and speed. Also how synchronized data sharing with stake holders can optimize closed loop corrective action, resources and quality.
{"title":"Manufacturing data: Maximizing value using component-to-system analysis","authors":"M. Kamm","doi":"10.1109/TEST.2009.5355834","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355834","url":null,"abstract":"This poster will provide a high-level description of Cisco's manufacturing process including how, where and in what form data is collected at various test steps. Trade offs are described to optimize test time and diagnostics for any failing parts in order to provide actionable data for failure analysis. The principal goal of the poster is to raise awareness regarding base component requirements for embedded instrumentation to allow for optimal diagnostic results and speed. Also how synchronized data sharing with stake holders can optimize closed loop corrective action, resources and quality.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134019546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355630
Chunhua Yao, K. Saluja, P. Ramanathan
We propose a test scheduling algorithm that ensures the resource compatibility and satisfies both power and thermal constraints. The proposed algorithm can start a test at an arbitrary time and it has the capability of delaying a test to let a core cool down to find a valid schedule even when traditional scheduling schemes cannot find a solution. To reduce the execution time of thermal simulation, we exploit superposition principle to compute the thermal profile rapidly and accurately. We apply our scheduling algorithm to ITC'02 SoC benchmarks and the results show a remarkable improvement in the total test length over other methods, while meeting the thermal and power constraints.
{"title":"Power and thermal constrained test scheduling","authors":"Chunhua Yao, K. Saluja, P. Ramanathan","doi":"10.1109/TEST.2009.5355630","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355630","url":null,"abstract":"We propose a test scheduling algorithm that ensures the resource compatibility and satisfies both power and thermal constraints. The proposed algorithm can start a test at an arbitrary time and it has the capability of delaying a test to let a core cool down to find a valid schedule even when traditional scheduling schemes cannot find a solution. To reduce the execution time of thermal simulation, we exploit superposition principle to compute the thermal profile rapidly and accurately. We apply our scheduling algorithm to ITC'02 SoC benchmarks and the results show a remarkable improvement in the total test length over other methods, while meeting the thermal and power constraints.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133111989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355836
S. Kannan, Bruce C. Kim
This paper describes a low cost test technique for testing Analog-Mixed Signal and RF load boards used in ATE (Automatic Test Equipment). The paper describes the development and application of a software tool for automatic analysis and test generation for mixed signal and RF circuits on Device Interface Boards (DIB). DIBs are essential components for testing ICs and they contain mixed-signal and RF circuits with several active and passive components that are needed to simulate test conditions for ICs. The software tool utilizes the schematic information of DIBs to generate tests for components and interconnectivity on the DIB. The tests generated are dependent upon the accessibility and programmability provided by the test hardware as well as the testability provided by DIB design. The output of the tool is a generic test specification that is independent of test hardware platform. Automatic test generation saves on the manual labor for writing DIB tests and thus contributing to the reduction of time to market for ICs.
{"title":"Automatic diagnostic tool for Analog-Mixed Signal and RF load boards","authors":"S. Kannan, Bruce C. Kim","doi":"10.1109/TEST.2009.5355836","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355836","url":null,"abstract":"This paper describes a low cost test technique for testing Analog-Mixed Signal and RF load boards used in ATE (Automatic Test Equipment). The paper describes the development and application of a software tool for automatic analysis and test generation for mixed signal and RF circuits on Device Interface Boards (DIB). DIBs are essential components for testing ICs and they contain mixed-signal and RF circuits with several active and passive components that are needed to simulate test conditions for ICs. The software tool utilizes the schematic information of DIBs to generate tests for components and interconnectivity on the DIB. The tests generated are dependent upon the accessibility and programmability provided by the test hardware as well as the testability provided by DIB design. The output of the tool is a generic test specification that is independent of test hardware platform. Automatic test generation saves on the manual labor for writing DIB tests and thus contributing to the reduction of time to market for ICs.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115358517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355682
O. Sinanoglu, S. Almukhaizim
Despite the advantages of performing response compaction in Integrated-Circuit (IC) testing, unknown response bits (x's) inevitably reflect into loss in test quality. The distribution of these x's within the captured response, which varies for each test pattern, directly impacts the number of scan cells observed through the response compactor. In this work, we propose a two-dimensional X-alignment technique in order to judiciously manipulate the distribution of x's in the test response prior to its compaction. The controlled response manipulation is performed on a per pattern basis, in the form of scan chain delay and intra-slice rotate operations, and with the objective that x's are aligned within as few scan slices and chains as possible. Consequently, a larger number of scan cells are observed after compaction for any test pattern. The computation of the control data, i.e., rotate and delay bits, is formulated as a MAX-SAT problem, and efficient heuristics are provided. The proposed technique is test set independent, leading to a generic, simple, and cost-effective hardware implementation. The X-alignment technique can be utilized with any response compactor to manipulate the x-distribution in favor of the compactor, thus improving the test quality.
{"title":"X-alignment techniques for improving the observability of response compactors","authors":"O. Sinanoglu, S. Almukhaizim","doi":"10.1109/TEST.2009.5355682","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355682","url":null,"abstract":"Despite the advantages of performing response compaction in Integrated-Circuit (IC) testing, unknown response bits (x's) inevitably reflect into loss in test quality. The distribution of these x's within the captured response, which varies for each test pattern, directly impacts the number of scan cells observed through the response compactor. In this work, we propose a two-dimensional X-alignment technique in order to judiciously manipulate the distribution of x's in the test response prior to its compaction. The controlled response manipulation is performed on a per pattern basis, in the form of scan chain delay and intra-slice rotate operations, and with the objective that x's are aligned within as few scan slices and chains as possible. Consequently, a larger number of scan cells are observed after compaction for any test pattern. The computation of the control data, i.e., rotate and delay bits, is formulated as a MAX-SAT problem, and efficient heuristics are provided. The proposed technique is test set independent, leading to a generic, simple, and cost-effective hardware implementation. The X-alignment technique can be utilized with any response compactor to manipulate the x-distribution in favor of the compactor, thus improving the test quality.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117227135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355721
L. Testa, H. Lapuyade, Y. Deval, O. Mazouffre, J. Carbonéro, J. Bégueret
In order to implement a Built-In Self-Test (BIST) strategy for a Radio Frequency (RF) LC-Voltage Controlled Oscillator (VCO) devoted to Wimax applications, an exhaustive study of the fault coverage achievable for this block is carried out. The peak-to-peak value of the output voltage is shown to be the best quantity to monitor. Once the fault is detected, it is shown that the BIST can be exploited as well to trigger a feedback allowing, in some cases, the self-correction of the VCO. The complete system is designed using the STM CMOS 65nm process.
{"title":"BIST scheme for RF VCOs allowing the self-correction of the cut","authors":"L. Testa, H. Lapuyade, Y. Deval, O. Mazouffre, J. Carbonéro, J. Bégueret","doi":"10.1109/TEST.2009.5355721","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355721","url":null,"abstract":"In order to implement a Built-In Self-Test (BIST) strategy for a Radio Frequency (RF) LC-Voltage Controlled Oscillator (VCO) devoted to Wimax applications, an exhaustive study of the fault coverage achievable for this block is carried out. The peak-to-peak value of the output voltage is shown to be the best quantity to monitor. Once the fault is detected, it is shown that the BIST can be exploited as well to trigger a feedback allowing, in some cases, the self-correction of the VCO. The complete system is designed using the STM CMOS 65nm process.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131454766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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