Low power multiplication for FIR filters

Abstract

This paper describes Booth encoded multipliers and their use in FIR filters and other DSP applications where one input is random and the other is highly correlated. Selecting the correct multiplier configuration for a given application can reduce power by more than 50% depending on the filter response. We show that applying the coefficients of an FIR filter to the Booth encoded input gives less switching activity in the multiplier than when applied to the multiplicand input. We also show that power savings are possible when using time-multiplexed multipliers to compute several filter taps. The techniques are supported with measurements from a full-custom adaptive equalizer chip for broadband communications.