Embedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability Improvement

Abstract

In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of the memory cell being upset. The current checking is performed on an H-tree SRAM in different ways. We demonstrate the assertions of the proposed technique by performing a reliability analysis while combining current monitoring with a single-parity bit or Hamming codes per RAM word to perform single or multiple error correction.