Implementation of application specific instruction-set processor for the artificial neural network acceleration using LISA ADL

Abstract

In fields like embedded vision, where algorithms are computationally expensive, hardware accelerators play a major role in high throughput applications. These accelerators could be implemented as hardwired IP cores or Application Specific Instruction-set Processors (ASIPs). While hardwired solutions often provide the best possible performance, they are less flexible then ASIP implementation. In this paper, we present a design flow of ASIP for feed-forward fully-connected neural network acceleration. Design was named Neural Network ASIP (NNAP) and developed using LISA language for ASIP, tested on Zynq7020 FPGA and finally, its performance was compared to the software solution running on the ARM Cortex-A9 core. It was shown that the performance of ASIP solution, running on Zynq FPGA, is approximately from 20 to 40 times faster when compared to the software implementation, running on the ARM based architecture.