{"title":"Tunable linear MOS resistor for RF applications","authors":"Xinbo Xiang, J. Sturm","doi":"10.1109/SIRF.2012.6160119","DOIUrl":null,"url":null,"abstract":"This paper discusses a continuously tunable linear MOS resistor with bi-directional characteristics. The proposal is based on a 2nd order nonlinearity cancellation and is implemented by quasi-floating-gate (QFG) technique. The resistor is optimized for speed, noise and linearity, which makes it well-suited for tunable RF amplifiers. Parallel slices were introduced to enlarge the tuning range. A switching strategy is implemented to guarantee monotonic tuning with limited linearity loss. A testchip is fabricated in 65nm CMOS technology, which shows a -40dB distortion with moderate overdrive voltage and 200mV peak to peak signal amplitude and a high tuning ratio of 19. This MOS resistor has no static power consumption and a layout area of 39μm × 37μm.","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"125 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIRF.2012.6160119","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
This paper discusses a continuously tunable linear MOS resistor with bi-directional characteristics. The proposal is based on a 2nd order nonlinearity cancellation and is implemented by quasi-floating-gate (QFG) technique. The resistor is optimized for speed, noise and linearity, which makes it well-suited for tunable RF amplifiers. Parallel slices were introduced to enlarge the tuning range. A switching strategy is implemented to guarantee monotonic tuning with limited linearity loss. A testchip is fabricated in 65nm CMOS technology, which shows a -40dB distortion with moderate overdrive voltage and 200mV peak to peak signal amplitude and a high tuning ratio of 19. This MOS resistor has no static power consumption and a layout area of 39μm × 37μm.
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