Research on Design and Verification of Sobel Image Edge Detection Based on High Level Synthesis

Abstract

Image edge detection technology is very important in the field of digital image processing, which is widely used in many fields,such as computer graphics processing, target matching, machine recognition, traffic control, national defense security and so on [1].Because of the complicated calculation steps of the image edge detection algorithm and the high processing speed requirements, it is difficult to meet the requirements only by software method, which is a problem of image edge detection. The design of FPGA can effectively solve the above disadvantages due to its parallelism and real-time performance, but the traditional FPGA development needs to master the hardware description language such as Verilog or VHDL design, which has long development cycles and high costs. In order to solve the above disadvantages effectively, this paper presents a method that using C and C++ language to develop Sobel algorithm by Vivado HLS(short for High Level Synthesis). The method can be implemented in FPGA design after High Level Synthesis, and provide a new design idea for software developers who are not familiar with the HDL language. Verified by theoretical analysis and simulation, using this algorithm can achieve a good image edge detection effect.