Zhipeng Li, Yan Li, Y. Avniel, A. Megretski, V. Stojanović
{"title":"Design trade-offs in signal component separators for outphasing power amplifiers","authors":"Zhipeng Li, Yan Li, Y. Avniel, A. Megretski, V. Stojanović","doi":"10.1109/ESSCIRC.2013.6649065","DOIUrl":null,"url":null,"abstract":"Implementation design space of piece-wise linear outphasing signal component separator is explored by utilizing the changes in micro-architecture, choice of storage elements and aggressive back-end leakage power optimization techniques. With combination of these techniques, ~2× energy and area savings are achieved, resulting in record energy-efficiency of 32pJ/sample for asymmetric multilevel outphasing and 22pJ/sample for linear amplification with nonlinear components, at throughput of 400MSample/s and areas of 0.2-0.4mm2 in 45nm SOI process.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 Proceedings of the ESSCIRC (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2013.6649065","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
Implementation design space of piece-wise linear outphasing signal component separator is explored by utilizing the changes in micro-architecture, choice of storage elements and aggressive back-end leakage power optimization techniques. With combination of these techniques, ~2× energy and area savings are achieved, resulting in record energy-efficiency of 32pJ/sample for asymmetric multilevel outphasing and 22pJ/sample for linear amplification with nonlinear components, at throughput of 400MSample/s and areas of 0.2-0.4mm2 in 45nm SOI process.