Low-Cost Concurrent Error Detection for FSMs Implemented Using Embedded Memory Blocks of FPGAs

2006 IEEE Design and Diagnostics of Electronic Circuits and systems Pub Date : 2006-04-18 DOI:10.1109/DDECS.2006.1649608

A. Krasniewski

引用次数: 5

Abstract

We present a number of low-cost concurrent error detection (CED) schemes for finite state machines (FSMs) implemented using embedded memory blocks available in FPGAs. The experimental results show that for many of the examined benchmark circuits, some of the proposed schemes provide for a reasonable level of error detection at a very low circuitry overhead, not exceeding 10%. The proposed set of CED schemes offers the designer an opportunity to trade-off error detection efficiency with implementation cost

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基于fpga嵌入式内存块的FSMs低成本并发错误检测

我们提出了一些低成本的并行错误检测(CED)方案，用于有限状态机(FSMs)，这些方案使用fpga中可用的嵌入式内存块实现。实验结果表明，对于许多测试的基准电路，一些提出的方案在非常低的电路开销(不超过10%)下提供了合理的错误检测水平。所提出的一组CED方案为设计者提供了一个权衡错误检测效率和实现成本的机会

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2006 IEEE Design and Diagnostics of Electronic Circuits and systems

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