Pub Date : 2006-04-18DOI: 10.1109/DDECS.2006.1649585
J. Bucek, R. Lórencz
This paper presents FPGA implementations of traditional almost Montgomery inverse and subtraction-free almost Montgomery inverse and compares their space and time properties. The subtraction-free algorithm with its hardware architecture overcomes the disadvantages of currently known methods (e.g. Gutub, et al., 2002). The ">" or "<" tests that require either extra clock cycles or extra chip area are completely eliminated
{"title":"Comparing Subtraction-Free and Traditional AMI","authors":"J. Bucek, R. Lórencz","doi":"10.1109/DDECS.2006.1649585","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649585","url":null,"abstract":"This paper presents FPGA implementations of traditional almost Montgomery inverse and subtraction-free almost Montgomery inverse and compares their space and time properties. The subtraction-free algorithm with its hardware architecture overcomes the disadvantages of currently known methods (e.g. Gutub, et al., 2002). The \">\" or \"<\" tests that require either extra clock cycles or extra chip area are completely eliminated","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115553793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-18DOI: 10.1109/DDECS.2006.1649615
M. García-Valderas, M. Portela-García, C. López-Ongil, L. Entrena
Fault injection is commonly used for evaluation of fault tolerance of safety-critical systems. Among the possible fault injection techniques, FPGA-based emulation is very attractive because of its superior performance. In particular, autonomous emulation technique can provide emulation speeds in the order of millions of faults per second. In this paper FPGA-based emulation is extended to circuits with embedded memories. To this purpose, an instrumented memory model is proposed that can be progressively enhanced to increase accuracy at the cost of a larger overhead. Also, an efficient fault injection mechanism is described. This model can be integrated in a seamless manner in an autonomous emulation system, as it is demonstrated using the LEON2 processor benchmark
{"title":"An Extension of Transient Fault Emulation Techniques to Circuits with Embedded Memories","authors":"M. García-Valderas, M. Portela-García, C. López-Ongil, L. Entrena","doi":"10.1109/DDECS.2006.1649615","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649615","url":null,"abstract":"Fault injection is commonly used for evaluation of fault tolerance of safety-critical systems. Among the possible fault injection techniques, FPGA-based emulation is very attractive because of its superior performance. In particular, autonomous emulation technique can provide emulation speeds in the order of millions of faults per second. In this paper FPGA-based emulation is extended to circuits with embedded memories. To this purpose, an instrumented memory model is proposed that can be progressively enhanced to increase accuracy at the cost of a larger overhead. Also, an efficient fault injection mechanism is described. This model can be integrated in a seamless manner in an autonomous emulation system, as it is demonstrated using the LEON2 processor benchmark","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123956420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-18DOI: 10.1109/DDECS.2006.1649617
J. Jaros, V. Dvorák
One-to-all broadcast (OAB) and all-to-all broadcast (AAB) (Defago, 2003) group communications are frequently used in many parallel algorithms and if their overhead is excessive, performance degrades rapidly with processor count. This paper deals with the design of a new application specific Bayesian optimization algorithm (BOA) and standard genetic algorithm (SGA) that both produce almost optimal communication schedules for an arbitrary multiprocessor topology. We demonstrated the optimization process on hypercube and AMP topology (Chalmers, 1996) using wormhole (WH) switching
{"title":"Evolutionary Design of OAB and AAB Communication Schedules for Networking Systems on Chips","authors":"J. Jaros, V. Dvorák","doi":"10.1109/DDECS.2006.1649617","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649617","url":null,"abstract":"One-to-all broadcast (OAB) and all-to-all broadcast (AAB) (Defago, 2003) group communications are frequently used in many parallel algorithms and if their overhead is excessive, performance degrades rapidly with processor count. This paper deals with the design of a new application specific Bayesian optimization algorithm (BOA) and standard genetic algorithm (SGA) that both produce almost optimal communication schedules for an arbitrary multiprocessor topology. We demonstrated the optimization process on hypercube and AMP topology (Chalmers, 1996) using wormhole (WH) switching","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132366612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-18DOI: 10.1109/DDECS.2006.1649568
Alex Ngouanga, G. Sassatelli, L. Torres, A. Soares, A. Susin
A homogeneous architecture made of an array of so-called NPUs (network processing units) is presented in this paper. Those NPUs are endowed with elementary processing and communication capabilities, that for exploring the opportunity of finely adapting system behavior according to current system state. Applications considered in this work are described as task graphs, which are mapped at run-time taking into account the performance requirements, the number of available NPUs and their respective positions. The placement is performed using different algorithms. An adaptive architecture running several MJPEG streaming applications is used for experiments and comparisons
{"title":"A contextual resources use: a proof of concept through the APACHES' platform","authors":"Alex Ngouanga, G. Sassatelli, L. Torres, A. Soares, A. Susin","doi":"10.1109/DDECS.2006.1649568","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649568","url":null,"abstract":"A homogeneous architecture made of an array of so-called NPUs (network processing units) is presented in this paper. Those NPUs are endowed with elementary processing and communication capabilities, that for exploring the opportunity of finely adapting system behavior according to current system state. Applications considered in this work are described as task graphs, which are mapped at run-time taking into account the performance requirements, the number of available NPUs and their respective positions. The placement is performed using different algorithms. An adaptive architecture running several MJPEG streaming applications is used for experiments and comparisons","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133388406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-18DOI: 10.1109/DDECS.2006.1649616
S. Yarmolik, B. Sokol
The goal of this paper is to propose a new technique for memory testing based on transparent memory march tests (van de Goor, 1991 and Nicolaidis, 1996). This paper deals with memory pattern sensitive faults detection problem. It shows the efficiency of multiple runs of march tests for memory passive pattern sensitive faults detection and analyzes the optimal address seeds for multiple march test runs. This paper provides only short fragment of carried researches. All results can be found in extended version of this paper
本文的目的是提出一种基于透明记忆行军测试的记忆测试新技术(van de Goor, 1991和Nicolaidis, 1996)。本文研究了记忆模式敏感故障检测问题。展示了多次行军测试对内存被动模式敏感故障检测的效率，并分析了多次行军测试的最优地址种子。本文只提供了所进行研究的一小部分。所有结果都可以在本文的扩展版中找到
{"title":"Optimal Memory Address Seeds for Pattern Sensitive Faults Detection","authors":"S. Yarmolik, B. Sokol","doi":"10.1109/DDECS.2006.1649616","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649616","url":null,"abstract":"The goal of this paper is to propose a new technique for memory testing based on transparent memory march tests (van de Goor, 1991 and Nicolaidis, 1996). This paper deals with memory pattern sensitive faults detection problem. It shows the efficiency of multiple runs of march tests for memory passive pattern sensitive faults detection and analyzes the optimal address seeds for multiple march test runs. This paper provides only short fragment of carried researches. All results can be found in extended version of this paper","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115597245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-18DOI: 10.1109/DDECS.2006.1649579
Tomáš Martínek, J. Korenek, Otto Fucík, M. Lexa
Systolic array architectures for approximate string matching play a significant role as hardware accelerators in biological applications. However, their wider use is limited by the lack of flexibility required by often variable tasks. In this respect, it is desirable to develop a procedure for automatic design and implementation of such accelerators to reach high performance and efficiency with as little human effort on the side of the designer as possible. This paper proposes the essential element of such procedure, a method for the calculation of generic systolic array parameters with respect to maximal performance and efficient resource utilization
{"title":"A flexible technique for the automatic design of approximate string matching architectures","authors":"Tomáš Martínek, J. Korenek, Otto Fucík, M. Lexa","doi":"10.1109/DDECS.2006.1649579","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649579","url":null,"abstract":"Systolic array architectures for approximate string matching play a significant role as hardware accelerators in biological applications. However, their wider use is limited by the lack of flexibility required by often variable tasks. In this respect, it is desirable to develop a procedure for automatic design and implementation of such accelerators to reach high performance and efficiency with as little human effort on the side of the designer as possible. This paper proposes the essential element of such procedure, a method for the calculation of generic systolic array parameters with respect to maximal performance and efficient resource utilization","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116851355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-18DOI: 10.1109/DDECS.2006.1649602
A. Benso, A. Bosio, S. Carlo, G. D. Natale, P. Prinetto
Among the different types of algorithms proposed to test static random access memories (SRAMs), march tests have proven to be faster, simpler and regularly structured. A large number of march tests with different fault coverage have been published. Usually different march tests detect only a specific set of memory faults. The always growing memory production technology introduces new classes of fault, making a key hurdle the generation of new march tests. The aim of this paper is to target the whole set of realistic fault model and to provide a unique march test able to reduce the test complexity of 15.4% than state-of-the-art march algorithm
{"title":"A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs","authors":"A. Benso, A. Bosio, S. Carlo, G. D. Natale, P. Prinetto","doi":"10.1109/DDECS.2006.1649602","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649602","url":null,"abstract":"Among the different types of algorithms proposed to test static random access memories (SRAMs), march tests have proven to be faster, simpler and regularly structured. A large number of march tests with different fault coverage have been published. Usually different march tests detect only a specific set of memory faults. The always growing memory production technology introduces new classes of fault, making a key hurdle the generation of new march tests. The aim of this paper is to target the whole set of realistic fault model and to provide a unique march test able to reduce the test complexity of 15.4% than state-of-the-art march algorithm","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116910068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-18DOI: 10.1109/DDECS.2006.1649583
Jaroslav Skarvada
This paper deals with test scheduling under power constraints. An approach based on genetic algorithm operating on test application conflict graph is presented. The main goal of the method is to minimize test application time with considering structural resource allocation conflicts and to ensure that test application schedule does not exceed chip power limits. The proposed method was implemented using C++, experimental results with ITC'02 SOC benchmark suite are presented in the paper together with the perspectives for the future research
{"title":"Test Scheduling for SOC under Power Constraints","authors":"Jaroslav Skarvada","doi":"10.1109/DDECS.2006.1649583","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649583","url":null,"abstract":"This paper deals with test scheduling under power constraints. An approach based on genetic algorithm operating on test application conflict graph is presented. The main goal of the method is to minimize test application time with considering structural resource allocation conflicts and to ensure that test application schedule does not exceed chip power limits. The proposed method was implemented using C++, experimental results with ITC'02 SOC benchmark suite are presented in the paper together with the perspectives for the future research","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128674931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-18DOI: 10.1109/DDECS.2006.1649614
J. M. Fernandes, Marcelino B. Santos, Arlindo L. Oliveira, João Paulo Teixeira
This work presents probabilistic methods for testability analysis at RTL and their use to guide DFT techniques like partial-scan and TPI. Controllability is analyzed using an approach that takes into account correlations within pre-defined groups formed based on an originally proposed heuristic. A method for observability computation at RTL based on the Boolean difference is presented. These testability analysis methods were implemented in a tool that reads a Verilog RTL description, solves the Chapman-Kolmogorov equations that describe the steady-state of the circuit, and outputs the computed values for the testability. A methodology for partial-scan and TPI optimization is proposed and implemented. The methodology is based on the testability metrics and on a "DFT dictionary". The proposed heuristic and methodology are evaluated using the ITC99 benchmark circuits
{"title":"Probabilistic Testability Analysis and DFT Methods at RTL","authors":"J. M. Fernandes, Marcelino B. Santos, Arlindo L. Oliveira, João Paulo Teixeira","doi":"10.1109/DDECS.2006.1649614","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649614","url":null,"abstract":"This work presents probabilistic methods for testability analysis at RTL and their use to guide DFT techniques like partial-scan and TPI. Controllability is analyzed using an approach that takes into account correlations within pre-defined groups formed based on an originally proposed heuristic. A method for observability computation at RTL based on the Boolean difference is presented. These testability analysis methods were implemented in a tool that reads a Verilog RTL description, solves the Chapman-Kolmogorov equations that describe the steady-state of the circuit, and outputs the computed values for the testability. A methodology for partial-scan and TPI optimization is proposed and implemented. The methodology is based on the testability metrics and on a \"DFT dictionary\". The proposed heuristic and methodology are evaluated using the ITC99 benchmark circuits","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127520534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-18DOI: 10.1109/DDECS.2006.1649581
H. Lampinen, Pauli Perälä, O. Vainio
This paper presents a scalable asynchronous dataflow processor. The main idea of the presented processor architecture is that the processing elements (PEs) are intelligent and can communicate directly with each other. A control element (CE) is used to solve possible conflicts between the data transferring of PEs and to control the execution of the program
{"title":"Design of a Scalable Asynchronous Dataflow Processor","authors":"H. Lampinen, Pauli Perälä, O. Vainio","doi":"10.1109/DDECS.2006.1649581","DOIUrl":"https://doi.org/10.1109/DDECS.2006.1649581","url":null,"abstract":"This paper presents a scalable asynchronous dataflow processor. The main idea of the presented processor architecture is that the processing elements (PEs) are intelligent and can communicate directly with each other. A control element (CE) is used to solve possible conflicts between the data transferring of PEs and to control the execution of the program","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133002164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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