Electrical, Thermal and Mechanical Simulation for Embedded Silicon Fan-out Wafer Level Packaging

Abstract

A novel embedded silicon fan-out wafer level packaging (eSiFO), which was proposed by Huatian Technology in 2015 and now in production, has a relatively simple manufacturing process eliminating molding and de-bonding process compared to typical fan-out process. This paper briefly introduces eSiFO technology at first, and then mainly studies its electrical and thermal performance, as well as RDL reliability. This study finds that eSiFO technology has a good package performance, and can further provide optimal performance for mobile electronics and potential IoT and 5G applications.