Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8705708
Fen Xia, Qingfeng Zhang, Yifan Chen, Bing Zhang
In this letter, we propose a wideband patch antenna for the head imaging systems. It is composed of a patch and the ground, and both structure are largely token off in comparison with normal patch antenna. By analyzing the structure of this antenna, we could obtain the band is mainly controlled by three parameters. Extensive simulations demonstrate that patch antenna provides wideband operation with −10 dB bandwidths of 71.1% at the frequency of 1.23 – 2.63 GHz. Moreover, the radiation patterns are almost the bi-directional and the gains are all above 3 dBi at entire operation frequencies.
{"title":"Design of Wideband Patch Antenna for Microwave Imaging Systems","authors":"Fen Xia, Qingfeng Zhang, Yifan Chen, Bing Zhang","doi":"10.1109/CICTA.2018.8705708","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8705708","url":null,"abstract":"In this letter, we propose a wideband patch antenna for the head imaging systems. It is composed of a patch and the ground, and both structure are largely token off in comparison with normal patch antenna. By analyzing the structure of this antenna, we could obtain the band is mainly controlled by three parameters. Extensive simulations demonstrate that patch antenna provides wideband operation with −10 dB bandwidths of 71.1% at the frequency of 1.23 – 2.63 GHz. Moreover, the radiation patterns are almost the bi-directional and the gains are all above 3 dBi at entire operation frequencies.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"19 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116686662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8705714
Shengzhou Zhang, Qiliang Li, Weifeng Zhu, Wanshun Jiang, F. Nian, Jianqin Deng
This paper presents a compact full W-band microwave monolithic integrated circuit (MMIC) low noise amplifier (LNA) using commercially 100nm GaAs pHEMTs technology. With a chip area of 1.1 mm$^{2}$, the circuit consists of 4 stages $4times30mu$m gate width transistors. The main performances of the full W-band LNA can be summarized as following: the peak gain of 22dB with 3dB bandwidth of 28GHz from 75GHz to 103GHz, where gain is higher than 17dB within the full W-band. The circuit exhibits the noise figure less than 4.5dB on the entire 75GHz-110GHz range and the minimum of 3.5dB at 82GHz. The input and output return losses are better than 6dB and 9dB on the full W-band, respectively. In conclusion, the LNA predicts outstanding figure-of-merits.
{"title":"A compact full W-band monolithic low noise amplifier for millimeter-wave imaging","authors":"Shengzhou Zhang, Qiliang Li, Weifeng Zhu, Wanshun Jiang, F. Nian, Jianqin Deng","doi":"10.1109/CICTA.2018.8705714","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8705714","url":null,"abstract":"This paper presents a compact full W-band microwave monolithic integrated circuit (MMIC) low noise amplifier (LNA) using commercially 100nm GaAs pHEMTs technology. With a chip area of 1.1 mm$^{2}$, the circuit consists of 4 stages $4times30mu$m gate width transistors. The main performances of the full W-band LNA can be summarized as following: the peak gain of 22dB with 3dB bandwidth of 28GHz from 75GHz to 103GHz, where gain is higher than 17dB within the full W-band. The circuit exhibits the noise figure less than 4.5dB on the entire 75GHz-110GHz range and the minimum of 3.5dB at 82GHz. The input and output return losses are better than 6dB and 9dB on the full W-band, respectively. In conclusion, the LNA predicts outstanding figure-of-merits.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127465813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706065
Zihan Luo, Jun Liu, Wenyong Zhou, Zhanfei Chen
Due to miniature dimension and limited thermal conductivity of silicon material, the performance of FinFETs is strongly influenced by self-heating effect, and is not suitable for conventional 1/f noise models. This study presents a new 1/f noise model for FinFETs to accommodate device temperature rise due to self-heating. This model can more realistically characterize the performance of small-size devices.
{"title":"An Improved 1/f Noise Model for FinFETs Accommodating Self-Heating Behaviors","authors":"Zihan Luo, Jun Liu, Wenyong Zhou, Zhanfei Chen","doi":"10.1109/CICTA.2018.8706065","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706065","url":null,"abstract":"Due to miniature dimension and limited thermal conductivity of silicon material, the performance of FinFETs is strongly influenced by self-heating effect, and is not suitable for conventional 1/f noise models. This study presents a new 1/f noise model for FinFETs to accommodate device temperature rise due to self-heating. This model can more realistically characterize the performance of small-size devices.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125736874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706046
Yan Yao, Zhiqun Li, Guoxiao Cheng, Lei Luo, Weipeng He, Qin Li
This paper presents a 6-18 GHz active 6-bit phase shifter based on a vector-sum technique in $0.13-mu m$ SiGe BiCMOS technology for X- and Ku-band phased arrays. An input Marchand balun and an L-C resonance-based quadrature all-pass filter are used to generate two orthogonal vectors with high $I/Q$ accuracy and high linearity over a wide frequency band. The $I/Q$ reference signals are then fed into two VGAs, of which the gains are adjusted with an integrated current-mode DAC to achieve the 6-bit phase resolution between $0-360^{o}$. The phase shifter shows 3.12 $dB$ of power gain at 9.25 GHz with a 3-dB gain bandwidth of 6.4-12.9 GHz, and the RMS gain variation is $lt 1.05 dB$ for all 6-bit phase states. The phase shifter achieves an input P1dB of $5-8dBm$ at 6-18 GHz for 0°-phase state. The measured RMS phase error is $lt 5.6^{o}$ at 5-18 GHz. The total current consumption is 28.2 $mA$ from a 3.3 V supply voltage and the overall chip size is $1.85times 1.32mm^{2}.$
{"title":"A 6-bit Active Phase Shifter for X- and Ku-band Phased Arrays","authors":"Yan Yao, Zhiqun Li, Guoxiao Cheng, Lei Luo, Weipeng He, Qin Li","doi":"10.1109/CICTA.2018.8706046","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706046","url":null,"abstract":"This paper presents a 6-18 GHz active 6-bit phase shifter based on a vector-sum technique in $0.13-mu m$ SiGe BiCMOS technology for X- and Ku-band phased arrays. An input Marchand balun and an L-C resonance-based quadrature all-pass filter are used to generate two orthogonal vectors with high $I/Q$ accuracy and high linearity over a wide frequency band. The $I/Q$ reference signals are then fed into two VGAs, of which the gains are adjusted with an integrated current-mode DAC to achieve the 6-bit phase resolution between $0-360^{o}$. The phase shifter shows 3.12 $dB$ of power gain at 9.25 GHz with a 3-dB gain bandwidth of 6.4-12.9 GHz, and the RMS gain variation is $lt 1.05 dB$ for all 6-bit phase states. The phase shifter achieves an input P1dB of $5-8dBm$ at 6-18 GHz for 0°-phase state. The measured RMS phase error is $lt 5.6^{o}$ at 5-18 GHz. The total current consumption is 28.2 $mA$ from a 3.3 V supply voltage and the overall chip size is $1.85times 1.32mm^{2}.$","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123423835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706083
Yuzi Song, Zhiliang Xia, Wen-yu Hua, F. Liu, Z. Huo
In this paper, complicated array leakage current of three-dimensional (3D) vertical channel NAND flash memory has been investigated and optimized. Monte Carlo simulation results show the design of channel hole layout, process variation of channel hole critical dimension are identified to the leakage issue. Experiment results show that the optimized layout, the elliptical outer hole profile and more uniform channel hole critical dimension lead to a significant leakage improvement.
{"title":"Modeling and optimization of Array Leakage in 3D NAND Flash Memory","authors":"Yuzi Song, Zhiliang Xia, Wen-yu Hua, F. Liu, Z. Huo","doi":"10.1109/CICTA.2018.8706083","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706083","url":null,"abstract":"In this paper, complicated array leakage current of three-dimensional (3D) vertical channel NAND flash memory has been investigated and optimized. Monte Carlo simulation results show the design of channel hole layout, process variation of channel hole critical dimension are identified to the leakage issue. Experiment results show that the optimized layout, the elliptical outer hole profile and more uniform channel hole critical dimension lead to a significant leakage improvement.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"613 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116453804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706027
L. Tai, Xiaoxin Xu, Peng Yuan, Jie Yu, Q. Luo, H. Lv, Ming Liu
In this work, we propose the TaON based RRAM with the structure of Ru/TaON/WOx/W through thermal oxidation process with plasma N2O. The TaON based devices show the low operation voltage $(lt1.8mathrm{V})$ without forming operation. Due to the nitrogen induced filament confinement, the variability and soft error during cycling are reduced. The TaON based RRAM also shows the excellent retention at 150 °C. The potential of the TaON based device on ultra-high density memory application inspires by the achievement of the multi-level storage by controlling the compliance current.
{"title":"A CMOS Compatible, Forming Free TaON-based ReRAM with Low Soft Errors and Good Retention!!","authors":"L. Tai, Xiaoxin Xu, Peng Yuan, Jie Yu, Q. Luo, H. Lv, Ming Liu","doi":"10.1109/CICTA.2018.8706027","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706027","url":null,"abstract":"In this work, we propose the TaON based RRAM with the structure of Ru/TaON/WOx/W through thermal oxidation process with plasma N2O. The TaON based devices show the low operation voltage $(lt1.8mathrm{V})$ without forming operation. Due to the nitrogen induced filament confinement, the variability and soft error during cycling are reduced. The TaON based RRAM also shows the excellent retention at 150 °C. The potential of the TaON based device on ultra-high density memory application inspires by the achievement of the multi-level storage by controlling the compliance current.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122989812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8705958
L. Zhao, Yujie Huang, Ming-e Jing, Xiaoyang Zeng, Yibo Fan
Image stitching is an important part of computer vision, and how to do it more efficiently with high quality is a heated topic. In this paper, the authors propose a new method called TMGA for image stitching to get an improved performance in calculating Transform Matrix by using Genetic Algorithm. The proposed TMGA not only counts the number of interior points, but also takes standard error and degree of dispersion into consideration compared the traditional methods. The results demonstrate that the proposed algorithm can gain a high-quality transform matrix and improves the result of the stitching.
{"title":"A Method of Using Genetic Algorithm in Image Stitching","authors":"L. Zhao, Yujie Huang, Ming-e Jing, Xiaoyang Zeng, Yibo Fan","doi":"10.1109/CICTA.2018.8705958","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8705958","url":null,"abstract":"Image stitching is an important part of computer vision, and how to do it more efficiently with high quality is a heated topic. In this paper, the authors propose a new method called TMGA for image stitching to get an improved performance in calculating Transform Matrix by using Genetic Algorithm. The proposed TMGA not only counts the number of interior points, but also takes standard error and degree of dispersion into consideration compared the traditional methods. The results demonstrate that the proposed algorithm can gain a high-quality transform matrix and improves the result of the stitching.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124756133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper analyzes temporal noise in the CMOS image sensor readout chain. The impact of column capacitors on input-referred noise is discussed as the column capacitors make a major contribution to the area of column circuits. Based on the analysis, a new low-noise design method for CMOS image sensors of cellphones is proposed. By implementing MOM capacitors in the pixel array, the area of column readout circuits is effectively reduced.
{"title":"Analysis and a Reduction Method of Temporal Noise in the CMOS Image Sensor Readout Chain","authors":"Jingwei Wei, Dongmei Li, Jingxuan Qiao, Lixin Zhao","doi":"10.1109/CICTA.2018.8705719","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8705719","url":null,"abstract":"This paper analyzes temporal noise in the CMOS image sensor readout chain. The impact of column capacitors on input-referred noise is discussed as the column capacitors make a major contribution to the area of column circuits. Based on the analysis, a new low-noise design method for CMOS image sensors of cellphones is proposed. By implementing MOM capacitors in the pixel array, the area of column readout circuits is effectively reduced.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126903592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706037
Xiaobing Ding, Liang Zhao, Jiaqi Yang, F. Lin
A 1.5 bit redundancy method is adopted to increase the conversion speed and decrease the power consumption of the DAC switching process. To further speed up the comparison cycle and reduce the variable parasitic capacitance that affect the linearity of the ADC, a monotonic switching down scheme combined with a PMOS-input-low-dynamic-offset (PILDO) comparator was proposed. An 8bit SAR ADC with 1.5 bit redundancy mechanism has been designed in 130nm CMOS SOI process, achieving a ENOB of 7.8 bit.
{"title":"An 8bit 100MHz SAR ADC with 1.5bit Redundancy Method used in Pipelined Structure","authors":"Xiaobing Ding, Liang Zhao, Jiaqi Yang, F. Lin","doi":"10.1109/CICTA.2018.8706037","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706037","url":null,"abstract":"A 1.5 bit redundancy method is adopted to increase the conversion speed and decrease the power consumption of the DAC switching process. To further speed up the comparison cycle and reduce the variable parasitic capacitance that affect the linearity of the ADC, a monotonic switching down scheme combined with a PMOS-input-low-dynamic-offset (PILDO) comparator was proposed. An 8bit SAR ADC with 1.5 bit redundancy mechanism has been designed in 130nm CMOS SOI process, achieving a ENOB of 7.8 bit.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127893953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8705945
Shang Hu, Rui Bai, Juncheng Wang, Xuefeng Chen, Jianxu Ma, Xin Wang, Yuanxi Zhang, Lei Wang, Y. Cai, Hao Yan, Jiangao Xuan, Yuan Li, M. Lu, Tao Xia, Liu Chang, Qi Nan, P. Chiang
A 25.78Gb/s optical transmitter with asymmetric equalizing driver and reference-less clock and data recovery (CDR) is presented in 40nm CMOS. A low power 3-tap asymmetric pulse-equalizer is proposed to extend bandwidth and compensate for the nonlinearity when using low-bandwidth 14Gb/s 850nm-VCSELs. A reference-less half-rate CDR with digital frequency-locked loop is integrated to recover the data and remove any input accumulated jitter. Measurement results demonstrate 25.78Gb/s optical link with error free operation (BER<10-12) over 100m fiber. Significant improvements are observed in the optical eye-opening, which increases the horizontal and vertical opening up to 25% and 15% respectively compared to the traditional pre-emphasis. The transmitter dissipates 280mW from 1.2V and 3.3V dual supplies, in which the VCSEL driver with equalizer consumes 128mW.
{"title":"A 25Gb/s Optical CDR + Driver Transmitter Using 14Gb/s VCSELs in 40nm-CMOS","authors":"Shang Hu, Rui Bai, Juncheng Wang, Xuefeng Chen, Jianxu Ma, Xin Wang, Yuanxi Zhang, Lei Wang, Y. Cai, Hao Yan, Jiangao Xuan, Yuan Li, M. Lu, Tao Xia, Liu Chang, Qi Nan, P. Chiang","doi":"10.1109/CICTA.2018.8705945","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8705945","url":null,"abstract":"A 25.78Gb/s optical transmitter with asymmetric equalizing driver and reference-less clock and data recovery (CDR) is presented in 40nm CMOS. A low power 3-tap asymmetric pulse-equalizer is proposed to extend bandwidth and compensate for the nonlinearity when using low-bandwidth 14Gb/s 850nm-VCSELs. A reference-less half-rate CDR with digital frequency-locked loop is integrated to recover the data and remove any input accumulated jitter. Measurement results demonstrate 25.78Gb/s optical link with error free operation (BER<10-12) over 100m fiber. Significant improvements are observed in the optical eye-opening, which increases the horizontal and vertical opening up to 25% and 15% respectively compared to the traditional pre-emphasis. The transmitter dissipates 280mW from 1.2V and 3.3V dual supplies, in which the VCSEL driver with equalizer consumes 128mW.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125669970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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