A 25ns 64K SRAM

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1984.1156703

T. Ozawa, S. Koshimaru, O. Kudo, H. Itoh, N. Harashima, N. Yasuoka, H. Asai, T. Yamanaka, S. Kikuchi

引用次数: 9

Abstract

A 25ns 64K×1 CMOS SRAM with a 30.9mm²chip size will be covered in this paper. P-well 11.5μm CMOS technology features a double metal poly load 4-transistor memory cell.

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25ns 64K SRAM

本文将介绍一个25ns 64K×1 CMOS SRAM，其芯片尺寸为30.9mm2。P-well 11.5μm CMOS技术具有双金属多负载4晶体管存储单元。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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