An FPGA based accelerator for SAT based combinational equivalence checking

Abstract

In this paper we present software/reconfigurable hardware SAT accelerator for combinational equivalence checking. The SAT binary clauses are mapped into an implication graph and the ternary clauses are kept in an indexed clause database and mapped into the clause evaluator and conflict detector implemented on FPGA. The validity of the proposed approach is shown through the ISCAS'85 benchmark circuits.