Software defined radio (SDR) is one of the key technologies in the wireless communication industry. A tier-3 SDR, or ideal software radio receiver is a device that performs all the demodulation (RF, IF and baseband) entirely in the digital domain. In this work we present the implementation and performance measurement of an AM receiver that belongs to this class of ideal software radios. The receiver is implemented in a field programmable gate array device.
{"title":"Tier 3 software defined AM radio","authors":"Jung Ko, V. Gaudet, R. Hang","doi":"10.1109/IWSOC.2005.31","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.31","url":null,"abstract":"Software defined radio (SDR) is one of the key technologies in the wireless communication industry. A tier-3 SDR, or ideal software radio receiver is a device that performs all the demodulation (RF, IF and baseband) entirely in the digital domain. In this work we present the implementation and performance measurement of an AM receiver that belongs to this class of ideal software radios. The receiver is implemented in a field programmable gate array device.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121812982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Network-on-chip (NoC) provides a network as a global communication platform for future SoC designs. Evaluating network architectures requires both synthetic workloads and application-oriented traffic. We present our traffic configuration methods that can be used to configure uniform and locality traffic as synthetic workloads, and to configure channel-based traffic for specific applications. We also illustrate the significance of applying these methods to configure traffic for network evaluation and system simulation. These traffic configuration methods have been integrated into our Nostrum NoC simulation environment.
{"title":"Traffic configuration for evaluating networks on chips","authors":"Zhonghai Lu, A. Jantsch","doi":"10.1109/IWSOC.2005.107","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.107","url":null,"abstract":"Network-on-chip (NoC) provides a network as a global communication platform for future SoC designs. Evaluating network architectures requires both synthetic workloads and application-oriented traffic. We present our traffic configuration methods that can be used to configure uniform and locality traffic as synthetic workloads, and to configure channel-based traffic for specific applications. We also illustrate the significance of applying these methods to configure traffic for network evaluation and system simulation. These traffic configuration methods have been integrated into our Nostrum NoC simulation environment.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125408824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Test generation is a highly complex and time-consuming task. In this work, we present a distributed method for combinational test generation. The method is based on a hybrid approach that combines both deterministic and genetic approaches. The deterministic phase is based on the D-algorithm and generates an initial set of test vectors that are evolved in the genetic phase in order to achieve high fault coverage in a short time. The algorithm is parallelized based on a cluster of workstations using the message passing interface (MPI) library. Several benchmark circuits were attempted, and favorable results comparisons are reported.
{"title":"A hybrid distributed test generation method using deterministic and genetic algorithms","authors":"H. Harmanani, Bassem Karablieh","doi":"10.1109/IWSOC.2005.13","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.13","url":null,"abstract":"Test generation is a highly complex and time-consuming task. In this work, we present a distributed method for combinational test generation. The method is based on a hybrid approach that combines both deterministic and genetic approaches. The deterministic phase is based on the D-algorithm and generates an initial set of test vectors that are evolved in the genetic phase in order to achieve high fault coverage in a short time. The algorithm is parallelized based on a cluster of workstations using the message passing interface (MPI) library. Several benchmark circuits were attempted, and favorable results comparisons are reported.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125535684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Il-Gu Lee, Heejung Yu, Sok-Kyu Lee, Jin Lee, Sin-Chong Park
As the design complexity and the number of gates per pin are increasing rapidly, functional verification has become a critical step in the development of a system-on-chip (SoC). Traditional verification techniques, such as simulation or emulation, cannot satisfy the debugging requirement and simulation speed. Among various verification technologies, pattern-based emulation provides the most efficient execution speed, but has limited observability due to the limit on the number of available pins and memory size. In addition, it takes a long time to dump patterns into memory. We propose an efficient pattern-based emulation approach that combines a cycle-based simulation, an input pattern reduction method based on coverage result, and an automatic pattern comparing scheme.
{"title":"Efficient pattern-based emulation for IEEE 802.11a baseband","authors":"Il-Gu Lee, Heejung Yu, Sok-Kyu Lee, Jin Lee, Sin-Chong Park","doi":"10.1109/IWSOC.2005.55","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.55","url":null,"abstract":"As the design complexity and the number of gates per pin are increasing rapidly, functional verification has become a critical step in the development of a system-on-chip (SoC). Traditional verification techniques, such as simulation or emulation, cannot satisfy the debugging requirement and simulation speed. Among various verification technologies, pattern-based emulation provides the most efficient execution speed, but has limited observability due to the limit on the number of available pins and memory size. In addition, it takes a long time to dump patterns into memory. We propose an efficient pattern-based emulation approach that combines a cycle-based simulation, an input pattern reduction method based on coverage result, and an automatic pattern comparing scheme.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114905208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents the synthesizable testbench architecture based on the defined instruction for standalone mode verification. The proposed testbench performs fast emulation with low resource and increases flexibility and reusability with variable description of instructions. To prove the performance of our testbench, we verified IEEE 802.11a PHY baseband system and compare with co-sim mode and modified co-sim mode emulation.
{"title":"Instruction based testbench architecture","authors":"Ho-Seok Choi, Seungbeom Lee, Sin-Chong Park","doi":"10.1109/IWSOC.2005.76","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.76","url":null,"abstract":"This paper presents the synthesizable testbench architecture based on the defined instruction for standalone mode verification. The proposed testbench performs fast emulation with low resource and increases flexibility and reusability with variable description of instructions. To prove the performance of our testbench, we verified IEEE 802.11a PHY baseband system and compare with co-sim mode and modified co-sim mode emulation.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"424 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116382443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Derakhshandeh, N. Masoumi, B. Kasiri, Y. Farazmand, Akbarzadeh, S. Aghnoot
Leakage current is becoming very important factor in determining the feasibility of designs, today. Due to exponential relationship between leakage current and threshold voltage in the weak inversion region, leakage power can no longer be ignored. In this paper we present a technique to accurately estimate leakage power by a linear model. In the first model the inputs are the number of all gates that used in circuit. And in the second model inputs are the number of gates and in the third model inputs are the number of input states of gates. The model is validated for a large benchmark circuits and the leakage power predicted by our model is within 5% of the actual leakage power predicted by a popular tool used in the industry.
{"title":"A precise model for leakage power estimation in VLSI circuits","authors":"J. Derakhshandeh, N. Masoumi, B. Kasiri, Y. Farazmand, Akbarzadeh, S. Aghnoot","doi":"10.1109/IWSOC.2005.23","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.23","url":null,"abstract":"Leakage current is becoming very important factor in determining the feasibility of designs, today. Due to exponential relationship between leakage current and threshold voltage in the weak inversion region, leakage power can no longer be ignored. In this paper we present a technique to accurately estimate leakage power by a linear model. In the first model the inputs are the number of all gates that used in circuit. And in the second model inputs are the number of gates and in the third model inputs are the number of input states of gates. The model is validated for a large benchmark circuits and the leakage power predicted by our model is within 5% of the actual leakage power predicted by a popular tool used in the industry.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128738393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recently, the video decoding players, such as DVD, VCD, have widely used. However, the image has large distortions as the decoding bit stream from damaged disks. In this study, we develop an error concealment processor for real-time video decoding systems. First, an efficiency algorithm is advised for error concealment with adaptations of the spatial interpolation and the temporal prediction. Based on the adaptive algorithm, real-time VLSI architecture is developed using cell-based design. The complex processing schedule for the error concealment processor is planned as integrated to video decoding systems. The chip occupies one line-buffer and about 27k logic gates using TSMC 0.35/spl mu/m process. The throughput rate of this error concealment chip can achieve about 50M pixels per second using about 9mm/sup 2/ silicon area.
{"title":"A high-performance error concealment processor for video decoder","authors":"Shih-Chang Hsia, S. Chou","doi":"10.1109/IWSOC.2005.12","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.12","url":null,"abstract":"Recently, the video decoding players, such as DVD, VCD, have widely used. However, the image has large distortions as the decoding bit stream from damaged disks. In this study, we develop an error concealment processor for real-time video decoding systems. First, an efficiency algorithm is advised for error concealment with adaptations of the spatial interpolation and the temporal prediction. Based on the adaptive algorithm, real-time VLSI architecture is developed using cell-based design. The complex processing schedule for the error concealment processor is planned as integrated to video decoding systems. The chip occupies one line-buffer and about 27k logic gates using TSMC 0.35/spl mu/m process. The throughput rate of this error concealment chip can achieve about 50M pixels per second using about 9mm/sup 2/ silicon area.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"318 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130541360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The advanced encryption standard makes repeated use of a performance limiting randomization step, SubBytes, which invokes an S-box logic junction to scramble 8 data inputs. This paper introduces a new method for implementing S-box (and a variant, called T-box) logic functions. The method is as fast as previous methods, but uses only one quarter of the gates of other fast methods. In addition, the method can produce a differential output which helps to speed up downstream exclusive-or logic.
{"title":"An area-efficient high-speed AES S-box method","authors":"R. Hobson, Scott Wakelin","doi":"10.1109/IWSOC.2005.37","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.37","url":null,"abstract":"The advanced encryption standard makes repeated use of a performance limiting randomization step, SubBytes, which invokes an S-box logic junction to scramble 8 data inputs. This paper introduces a new method for implementing S-box (and a variant, called T-box) logic functions. The method is as fast as previous methods, but uses only one quarter of the gates of other fast methods. In addition, the method can produce a differential output which helps to speed up downstream exclusive-or logic.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129092821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Nowadays, with high demand of very large scale integration (VLSI) design and also high work frequency for circuits, the related issues such as noise cancellation, reduction, and modeling have become more important. In order to overcome the power supply noise problem, in the floorplanning level, this paper develops a mixed algorithm employing the priority-based max-flow algorithm, and decoupling capacitance insertion technique. We used this new algorithm, as a part of a floorplanner and extract the floorplan considering several objectives. A variety of important objectives are: optimum area, wire length, power supply noise reduction, and power supply network design.
{"title":"A stochastic power-supply noise reduction technique using max-flow algorithm and decoupling capacitance","authors":"S. A. Moghaddam, N. Masoumi, C. Lucas","doi":"10.1109/IWSOC.2005.28","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.28","url":null,"abstract":"Nowadays, with high demand of very large scale integration (VLSI) design and also high work frequency for circuits, the related issues such as noise cancellation, reduction, and modeling have become more important. In order to overcome the power supply noise problem, in the floorplanning level, this paper develops a mixed algorithm employing the priority-based max-flow algorithm, and decoupling capacitance insertion technique. We used this new algorithm, as a part of a floorplanner and extract the floorplan considering several objectives. A variety of important objectives are: optimum area, wire length, power supply noise reduction, and power supply network design.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123993291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper summarizes the activities of next generation SERDES based interconnect standards and give a review of next generation Telecom, datacom and storage based SERDES interfaces. It discusses new techniques being developed for specifying interconnect operation at 10Gbps speeds over 'challenging' channels.
{"title":"A review of current standards activities for high speed physical layers","authors":"T. Palkert","doi":"10.1109/IWSOC.2005.25","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.25","url":null,"abstract":"This paper summarizes the activities of next generation SERDES based interconnect standards and give a review of next generation Telecom, datacom and storage based SERDES interfaces. It discusses new techniques being developed for specifying interconnect operation at 10Gbps speeds over 'challenging' channels.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127773015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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