T. Manku, C. Snyder, Michele Ting, Y. Ling, J. Khajehpour, Bill Kung, L. Wong
{"title":"Dual mixer downconversion architecture using complex mixing signals: enabling solutions for software defined radios","authors":"T. Manku, C. Snyder, Michele Ting, Y. Ling, J. Khajehpour, Bill Kung, L. Wong","doi":"10.1109/CICC.2002.1012802","DOIUrl":null,"url":null,"abstract":"A dual mixer architecture using complex mixing functions to perform RF downconversion is described. This architecture eliminates the need for the image-reject and IF filters present in the heterodyne architecture, while achieving better LO leakage, 1/f noise. and second-order intercept performance than the direct conversion architecture. This architecture, implemented in a 1.8 V, 0.18 /spl mu/m CMOS process, achieves a maximum IIP2 of 85 dBm, a baseband 1/f noise corner frequency of less than 100 kHz, a LO-RF leakage equaling -138 dBm, and an operating frequency ranging from 400 MHz to 2.5 GHz.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2002.1012802","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
A dual mixer architecture using complex mixing functions to perform RF downconversion is described. This architecture eliminates the need for the image-reject and IF filters present in the heterodyne architecture, while achieving better LO leakage, 1/f noise. and second-order intercept performance than the direct conversion architecture. This architecture, implemented in a 1.8 V, 0.18 /spl mu/m CMOS process, achieves a maximum IIP2 of 85 dBm, a baseband 1/f noise corner frequency of less than 100 kHz, a LO-RF leakage equaling -138 dBm, and an operating frequency ranging from 400 MHz to 2.5 GHz.