Noise-Aware On-Chip Power Grid Considerations Using a Statistical Approach

Abstract

We analyze the correlation between different parameters of the on-chip power distribution grid and their impact on noise. By using factor analysis we are able to uncover correlations between power grid design variables and power supply noise. We derive the correlation between design variables and noise from an analysis of 300 different grids in a 65-nm process technology, and manage to find the impact that a change in power grid design variables will have on noise. The results from this analysis can be used as guidelines when designing a robust power distribution grid.