Design of CMOS integrated circuits for radiation hardening and its application to space electronics

Abstract

This paper addresses some design tricks that allow canceling - or at least reducing - the sensitivity of silicon integrated circuits to radiation effects. Both analog and digital circuits are here addressed. Redundancy, specific topology, system-level compensation: any combination is helpful as long as it avoids the implementation of radiation hardened specific technologies, as these are both expensive and unsuited to most of the state-of-the-art building blocks.