{"title":"Design for failure analysis inserting replacement-type observation points for LVP","authors":"J. Nonaka, T. Ishiyama, Kazuki Shigeta","doi":"10.1109/TEST.2009.5355707","DOIUrl":null,"url":null,"abstract":"The method to insert observation points by replacing cells is proposed for laser voltage probing (LVP) measurements to ease failure analysis. Also proposed are a model of delay change with placing observation points and its insertion procedure that minimizes the number of timing violations. Evaluation in a commercial product circuit shows that “replacement-type” observation points can be inserted efficiently on critical paths which left less setup margin to insert “additional-type” ones. The number of timing violations caused insertion is a little and those can be easily fixed by using proposed delay model. The proposed method is thus practical for commercial product design and effective for delay fault analysis. This application will be attractive to find defects in complicated VLSI circuits because failure analysis becomes more difficult to downsize transistors smaller than the resolution of the failure analysis equipments such as LVP.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"73 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Test Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.2009.5355707","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
The method to insert observation points by replacing cells is proposed for laser voltage probing (LVP) measurements to ease failure analysis. Also proposed are a model of delay change with placing observation points and its insertion procedure that minimizes the number of timing violations. Evaluation in a commercial product circuit shows that “replacement-type” observation points can be inserted efficiently on critical paths which left less setup margin to insert “additional-type” ones. The number of timing violations caused insertion is a little and those can be easily fixed by using proposed delay model. The proposed method is thus practical for commercial product design and effective for delay fault analysis. This application will be attractive to find defects in complicated VLSI circuits because failure analysis becomes more difficult to downsize transistors smaller than the resolution of the failure analysis equipments such as LVP.