Chak-Wa Pui, Gang Wu, Freddy Y. C. Mang, Evangeline F. Y. Young
{"title":"An Analytical Approach for Time-Division Multiplexing Optimization in Multi-FPGA based Systems","authors":"Chak-Wa Pui, Gang Wu, Freddy Y. C. Mang, Evangeline F. Y. Young","doi":"10.1109/SLIP.2019.8771330","DOIUrl":null,"url":null,"abstract":"To increase the utilization of FPGAs in multi-FPGA based systems, time-division multiplexing (TDM) is a widely used technique to accommodate a large number of inter-FPGA signals. However, with this technique, the delay imposed by the inter-FPGA connections becomes significant. Previous research shows that TDM ratio of signals can greatly affect the performance of a system. In this paper, we extend previous problem formulation to meet more general constraints in multi-FPGA based systems and propose a novel approach to solve it. In particular, to optimize system clock period effectively and efficiently, we propose a two-step analytical framework, which first gives a continuous result using a non-linear conjugate gradient-based method and then finalizes the result optimally by a dynamic programming-based discretization algorithm. For comparison, we also solve the problem using an integer linear programming (ILP)-based method. Experimental results show that our approach can improve the system clock period by about 7% on top of a well optimized inter-FPGA routing result. Moreover, our approach scales for designs over 400K nodes while ILP-based method is not able to finish for designs with 2K nodes.","PeriodicalId":340036,"journal":{"name":"2019 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SLIP.2019.8771330","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
To increase the utilization of FPGAs in multi-FPGA based systems, time-division multiplexing (TDM) is a widely used technique to accommodate a large number of inter-FPGA signals. However, with this technique, the delay imposed by the inter-FPGA connections becomes significant. Previous research shows that TDM ratio of signals can greatly affect the performance of a system. In this paper, we extend previous problem formulation to meet more general constraints in multi-FPGA based systems and propose a novel approach to solve it. In particular, to optimize system clock period effectively and efficiently, we propose a two-step analytical framework, which first gives a continuous result using a non-linear conjugate gradient-based method and then finalizes the result optimally by a dynamic programming-based discretization algorithm. For comparison, we also solve the problem using an integer linear programming (ILP)-based method. Experimental results show that our approach can improve the system clock period by about 7% on top of a well optimized inter-FPGA routing result. Moreover, our approach scales for designs over 400K nodes while ILP-based method is not able to finish for designs with 2K nodes.