Pub Date : 2019-06-01DOI: 10.1109/SLIP.2019.8771331
Zheng Xu, J. Abraham
Functional safety is the top priority for the design of automotive and other mission-critical systems. We proposed Functional Safe NoC (FSNoC) with a new Packet Level Lock Stepping (PLLS) concept for Concurrent Error Detection (CED) of Network-on-Chip (NoC) with high Diagnostic Coverage (DC) and reduced area overhead. Furthermore, we proposed to divide the NoC network of a System-On-Chip(SOC) design into partitions with different performance requirements and apply separate but inter-operable safety mechanisms based on Performance Power Area (PPA) trade-off given the design meet safety requirement. The proposed techniques were used on an industry NoC design to achieve over 99% DC coverage with 11–33% of area, 12–29% power overhead and 5–22% of wiring overhead depending on partition choices.
{"title":"FSNoC: Safe Network-on-Chip Design with Packet Level Lock Stepping","authors":"Zheng Xu, J. Abraham","doi":"10.1109/SLIP.2019.8771331","DOIUrl":"https://doi.org/10.1109/SLIP.2019.8771331","url":null,"abstract":"Functional safety is the top priority for the design of automotive and other mission-critical systems. We proposed Functional Safe NoC (FSNoC) with a new Packet Level Lock Stepping (PLLS) concept for Concurrent Error Detection (CED) of Network-on-Chip (NoC) with high Diagnostic Coverage (DC) and reduced area overhead. Furthermore, we proposed to divide the NoC network of a System-On-Chip(SOC) design into partitions with different performance requirements and apply separate but inter-operable safety mechanisms based on Performance Power Area (PPA) trade-off given the design meet safety requirement. The proposed techniques were used on an industry NoC design to achieve over 99% DC coverage with 11–33% of area, 12–29% power overhead and 5–22% of wiring overhead depending on partition choices.","PeriodicalId":340036,"journal":{"name":"2019 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114876022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.1109/SLIP.2019.8771333
Dylan C. Stow, Itir Akgun, Yuan Xie
Interposer-based packaging is becoming a widespread methodology for tightly integrating multiple heterogeneous dies into a single package, with the potential to improve manufacturing yield and build larger-than-reticle-sized systems. However, interposer integration also introduces possible communication bottlenecks and cost overheads that can outweigh these benefits. To avoid these drawbacks, the abundant interposer interconnect can be leveraged as network-on-chip interconnection fabric to provide high-bandwidth, low-latency communication between chiplets and memory stacks. This work investigates this new interposer design space of passive and active interposer technologies, network-on-chip topologies, and clocking schemes to determine the cost-optimal interposer architectures for a range of performance requirements.
{"title":"Investigation of Cost-Optimal Network-on-Chip for Passive and Active Interposer Systems","authors":"Dylan C. Stow, Itir Akgun, Yuan Xie","doi":"10.1109/SLIP.2019.8771333","DOIUrl":"https://doi.org/10.1109/SLIP.2019.8771333","url":null,"abstract":"Interposer-based packaging is becoming a widespread methodology for tightly integrating multiple heterogeneous dies into a single package, with the potential to improve manufacturing yield and build larger-than-reticle-sized systems. However, interposer integration also introduces possible communication bottlenecks and cost overheads that can outweigh these benefits. To avoid these drawbacks, the abundant interposer interconnect can be leveraged as network-on-chip interconnection fabric to provide high-bandwidth, low-latency communication between chiplets and memory stacks. This work investigates this new interposer design space of passive and active interposer technologies, network-on-chip topologies, and clocking schemes to determine the cost-optimal interposer architectures for a range of performance requirements.","PeriodicalId":340036,"journal":{"name":"2019 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132978753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.1109/SLIP.2019.8771328
Farid Kenarangi, Inna Partin-Vaisband
Hardware security is a critical concern in design and fabrication of integrated circuits (ICs). Contemporary hardware threats comprise tens of advance invasive and non-invasive attacks for compromising security of modern ICs. Numerous attack-specific countermeasures against the individual threats have been proposed, trading power, area, speed, and design complexity of a system for security. These typical overheads combined with strict performance requirements in advanced technology nodes and high complexity of modern ICs often make the codesign of multiple countermeasures impractical. In this paper, on-chip distribution networks are exploited for detecting those hardware security threats that require non-invasive, yet physical interaction with an operating device-under-attack (e.g., measuring equipment for collecting sensitive information in side-channel attacks). With the proposed approach, the effect of the malicious physical interference with the device-under-attack is captured in the form of on-chip voltage variations and utilized for detecting malicious activity in the compromised device. A machine learning (ML) security IC is trained to predict system security based on sensed variations of signals within on-chip distribution networks. The trained ML ICs are distributed on-chip, yielding a robust and high-confidence security network on-chip. To halt an active attack, a variety of desired counteractions can be executed in a cost-effective manner upon the attack detection. The applicability and effectiveness of these security networks is demonstrated in this paper with respect to power, timing, and electromagnetic analysis attacks.
{"title":"Security Network On-Chip for Mitigating Side-Channel Attacks","authors":"Farid Kenarangi, Inna Partin-Vaisband","doi":"10.1109/SLIP.2019.8771328","DOIUrl":"https://doi.org/10.1109/SLIP.2019.8771328","url":null,"abstract":"Hardware security is a critical concern in design and fabrication of integrated circuits (ICs). Contemporary hardware threats comprise tens of advance invasive and non-invasive attacks for compromising security of modern ICs. Numerous attack-specific countermeasures against the individual threats have been proposed, trading power, area, speed, and design complexity of a system for security. These typical overheads combined with strict performance requirements in advanced technology nodes and high complexity of modern ICs often make the codesign of multiple countermeasures impractical. In this paper, on-chip distribution networks are exploited for detecting those hardware security threats that require non-invasive, yet physical interaction with an operating device-under-attack (e.g., measuring equipment for collecting sensitive information in side-channel attacks). With the proposed approach, the effect of the malicious physical interference with the device-under-attack is captured in the form of on-chip voltage variations and utilized for detecting malicious activity in the compromised device. A machine learning (ML) security IC is trained to predict system security based on sensed variations of signals within on-chip distribution networks. The trained ML ICs are distributed on-chip, yielding a robust and high-confidence security network on-chip. To halt an active attack, a variety of desired counteractions can be executed in a cost-effective manner upon the attack detection. The applicability and effectiveness of these security networks is demonstrated in this paper with respect to power, timing, and electromagnetic analysis attacks.","PeriodicalId":340036,"journal":{"name":"2019 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122623516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.1109/SLIP.2019.8771326
Boris Vaisband, S. Iyer
Silicon interconnect fabric (Si-IF) is a heterogeneous integration platform for ultra-large systems. Unpackaged dies are attached directly to a Si wafer at fine vertical interconnect pitch (2 to 10 μm) and small inter-die spacing (≤ 100 μm). The Si-IF replaces conventional interposers, packages, and printed circuit boards, and provides a single-hierarchy integration construct. Communication on the Si-IF platform is a key system-level challenge. Various approaches for local, semi-global (regional), and global communication are discussed in this paper. A network on interconnect fabric, based on intelligent utility dies, to support various system-level services, including communication, is introduced. Binning of communication schemes based on simulations of latency and energy is performed. A related design space, evaluated in terms of energy-latency product, with respect to distance is offered. Finally, external communication aspects are also discussed.
{"title":"Communication Considerations for Silicon Interconnect Fabric","authors":"Boris Vaisband, S. Iyer","doi":"10.1109/SLIP.2019.8771326","DOIUrl":"https://doi.org/10.1109/SLIP.2019.8771326","url":null,"abstract":"Silicon interconnect fabric (Si-IF) is a heterogeneous integration platform for ultra-large systems. Unpackaged dies are attached directly to a Si wafer at fine vertical interconnect pitch (2 to 10 μm) and small inter-die spacing (≤ 100 μm). The Si-IF replaces conventional interposers, packages, and printed circuit boards, and provides a single-hierarchy integration construct. Communication on the Si-IF platform is a key system-level challenge. Various approaches for local, semi-global (regional), and global communication are discussed in this paper. A network on interconnect fabric, based on intelligent utility dies, to support various system-level services, including communication, is introduced. Binning of communication schemes based on simulations of latency and energy is performed. A related design space, evaluated in terms of energy-latency product, with respect to distance is offered. Finally, external communication aspects are also discussed.","PeriodicalId":340036,"journal":{"name":"2019 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124411709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.1109/SLIP.2019.8771330
Chak-Wa Pui, Gang Wu, Freddy Y. C. Mang, Evangeline F. Y. Young
To increase the utilization of FPGAs in multi-FPGA based systems, time-division multiplexing (TDM) is a widely used technique to accommodate a large number of inter-FPGA signals. However, with this technique, the delay imposed by the inter-FPGA connections becomes significant. Previous research shows that TDM ratio of signals can greatly affect the performance of a system. In this paper, we extend previous problem formulation to meet more general constraints in multi-FPGA based systems and propose a novel approach to solve it. In particular, to optimize system clock period effectively and efficiently, we propose a two-step analytical framework, which first gives a continuous result using a non-linear conjugate gradient-based method and then finalizes the result optimally by a dynamic programming-based discretization algorithm. For comparison, we also solve the problem using an integer linear programming (ILP)-based method. Experimental results show that our approach can improve the system clock period by about 7% on top of a well optimized inter-FPGA routing result. Moreover, our approach scales for designs over 400K nodes while ILP-based method is not able to finish for designs with 2K nodes.
{"title":"An Analytical Approach for Time-Division Multiplexing Optimization in Multi-FPGA based Systems","authors":"Chak-Wa Pui, Gang Wu, Freddy Y. C. Mang, Evangeline F. Y. Young","doi":"10.1109/SLIP.2019.8771330","DOIUrl":"https://doi.org/10.1109/SLIP.2019.8771330","url":null,"abstract":"To increase the utilization of FPGAs in multi-FPGA based systems, time-division multiplexing (TDM) is a widely used technique to accommodate a large number of inter-FPGA signals. However, with this technique, the delay imposed by the inter-FPGA connections becomes significant. Previous research shows that TDM ratio of signals can greatly affect the performance of a system. In this paper, we extend previous problem formulation to meet more general constraints in multi-FPGA based systems and propose a novel approach to solve it. In particular, to optimize system clock period effectively and efficiently, we propose a two-step analytical framework, which first gives a continuous result using a non-linear conjugate gradient-based method and then finalizes the result optimally by a dynamic programming-based discretization algorithm. For comparison, we also solve the problem using an integer linear programming (ILP)-based method. Experimental results show that our approach can improve the system clock period by about 7% on top of a well optimized inter-FPGA routing result. Moreover, our approach scales for designs over 400K nodes while ILP-based method is not able to finish for designs with 2K nodes.","PeriodicalId":340036,"journal":{"name":"2019 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115432305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.1109/SLIP.2019.8771332
Ali Vosoughi, Longfei Wang, Selçuk Köse
Bus-invert coding technique is utilized to increase the security of cryptographic circuits (CC) against correlation power analysis attacks. The bus-invert coding technique is suitable to demolish the bijective relationship between the key and leakage information, making it difficult for a side-channel attacker to use correlation power analysis to obtain a secret key. The evaluations show that the number of measurements required to disclose the correct key (MTD) on the CC with bus-invert coding increases by more than 571X as compared to a naive CC, while the power consumption of the CC is reduced by 0.91 per cent.
{"title":"Bus-Invert Coding as a Low-Power Countermeasure Against Correlation Power Analysis Attack","authors":"Ali Vosoughi, Longfei Wang, Selçuk Köse","doi":"10.1109/SLIP.2019.8771332","DOIUrl":"https://doi.org/10.1109/SLIP.2019.8771332","url":null,"abstract":"Bus-invert coding technique is utilized to increase the security of cryptographic circuits (CC) against correlation power analysis attacks. The bus-invert coding technique is suitable to demolish the bijective relationship between the key and leakage information, making it difficult for a side-channel attacker to use correlation power analysis to obtain a secret key. The evaluations show that the number of measurements required to disclose the correct key (MTD) on the CC with bus-invert coding increases by more than 571X as compared to a naive CC, while the power consumption of the CC is reduced by 0.91 per cent.","PeriodicalId":340036,"journal":{"name":"2019 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125443888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.1109/SLIP.2019.8771327
Longfei Wang, Ragh Kuttappa, B. Taskin, Selçuk Köse
Digital low-dropout regulators (DLDOs) have been drawing significant attention within modern integrated systems such as processors and Internet of Things (IoT) devices. Despite the advantages of low design complexity, low voltage operation capability, and fast transient response, the inherent limit cycle oscillation of DLDOs lead to undesirable output voltage ripple at steady state. On the other hand, distributed on-chip voltage regulation with multiple tiny voltage regulators distributed across the chip achieves superior on-chip voltage noise profile. In this work, distributed DLDOs with phase interleaving are exploited to mitigate on-chip voltage noise due to limit cycle oscillation. Resonant rotary clock (ReRoC) is leveraged for robust clock generation and distribution. It is demonstrated through theoretical analysis and extensive simulations that significant on-chip voltage noise reduction can be achieved with the proposed technique.
{"title":"Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation","authors":"Longfei Wang, Ragh Kuttappa, B. Taskin, Selçuk Köse","doi":"10.1109/SLIP.2019.8771327","DOIUrl":"https://doi.org/10.1109/SLIP.2019.8771327","url":null,"abstract":"Digital low-dropout regulators (DLDOs) have been drawing significant attention within modern integrated systems such as processors and Internet of Things (IoT) devices. Despite the advantages of low design complexity, low voltage operation capability, and fast transient response, the inherent limit cycle oscillation of DLDOs lead to undesirable output voltage ripple at steady state. On the other hand, distributed on-chip voltage regulation with multiple tiny voltage regulators distributed across the chip achieves superior on-chip voltage noise profile. In this work, distributed DLDOs with phase interleaving are exploited to mitigate on-chip voltage noise due to limit cycle oscillation. Resonant rotary clock (ReRoC) is leveraged for robust clock generation and distribution. It is demonstrated through theoretical analysis and extensive simulations that significant on-chip voltage noise reduction can be achieved with the proposed technique.","PeriodicalId":340036,"journal":{"name":"2019 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124393345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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