{"title":"Energy efficient cache timing with performance bound","authors":"Leipo Yan, S. Lam, T. Srikanthan, W. Jigang","doi":"10.1109/DELTA.2006.45","DOIUrl":null,"url":null,"abstract":"Cache memories are the bottle-necks that limit the performance of the processors. In this paper, we present a heuristic algorithm for tuning the level-1 cache. The tuning method searches for the most energy efficient cache configuration under application performance requirement. By simulations we show that the proposed heuristic tuning algorithm is able to find the optimal or near optimal configurations. An algorithm for reducing the number of searched configurations is also proposed.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DELTA.2006.45","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Cache memories are the bottle-necks that limit the performance of the processors. In this paper, we present a heuristic algorithm for tuning the level-1 cache. The tuning method searches for the most energy efficient cache configuration under application performance requirement. By simulations we show that the proposed heuristic tuning algorithm is able to find the optimal or near optimal configurations. An algorithm for reducing the number of searched configurations is also proposed.
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