{"title":"Power Systems on Chiplet: Inductor-Linked Multi-Output Switched-Capacitor Multi-Rail Power Delivery on Chiplets","authors":"Mian Liao, Daniel H. Zhou, P. Wang, Minjie Chen","doi":"10.1109/3D-PEIM55914.2023.10052630","DOIUrl":null,"url":null,"abstract":"The energy demand of future computing introduces new challenges in voltage regulator design. This paper explores an inductor-linked single-input multi-output hybrid switched-capacitor power architecture with modular output cells for 48-V to point-of-load (PoL) chiplet power delivery. The unique inductor-linked configuration of switched-capacitor circuits enables high performance with a high voltage conversion ratio while achieving high efficiency and high power density. The architecture can be used, for example, to support multiple loads in a chiplet with many voltage rails from a high voltage input.","PeriodicalId":106578,"journal":{"name":"2023 Fourth International Symposium on 3D Power Electronics Integration and Manufacturing (3D-PEIM)","volume":"123 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 Fourth International Symposium on 3D Power Electronics Integration and Manufacturing (3D-PEIM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/3D-PEIM55914.2023.10052630","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract
The energy demand of future computing introduces new challenges in voltage regulator design. This paper explores an inductor-linked single-input multi-output hybrid switched-capacitor power architecture with modular output cells for 48-V to point-of-load (PoL) chiplet power delivery. The unique inductor-linked configuration of switched-capacitor circuits enables high performance with a high voltage conversion ratio while achieving high efficiency and high power density. The architecture can be used, for example, to support multiple loads in a chiplet with many voltage rails from a high voltage input.
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