Robust clock tree using single-well cells for multi-VT 28nm UTBB FD-SOI digital circuits

Abstract

The 28nm UTBB FD-SOI design platform enables multi-VT standard cells co-integration with independent back biases (BB). In this paper, we propose a new clock-tree cell to build a robust clock tree isolated from the various BB of the different Vt regions, showing better propagation and transition times balancing (2.5x), and a drastic skew reduction (5x at 0.4V) compared to a conventional clock tree.