Digital Sianal Processing And Image Processing

Abstract

The first paper, A Versatile and Scalable MIMD Architecture for Use as a Key Component in Studio Quality Motion Estimation System, describes an ASIC implementation of a scalable multiprocessor architecture dedicated to perform motion estimation on MPEG-2 CCIR 60 1 sequences. Its flexibility and scalability are key to the author’s goal for reusability in the face of changing requirements. Paper two describes A Single Chip Video Coding System With Embedded DRAM Frame Memories for Stand-Alone Applications. This ASIC can be adapted to various image CODEC standards and can be fabricated to allow for different sized images. The third paper, A Flexible Pipelined Image Processor, also emphasizes flexibility in the types of operations that can be performed. This ASIC performs operations including histogramming, image modification, convolution, halftone, error diffusion, and thresholding.