On test compaction objectives for combinational and sequential circuits

Abstract

We study storage schemes for test patterns and test responses of combinational and synchronous sequential circuits which are tested off-line by a tester. These storage schemes provide new objectives for test compaction beyond the need to reduce the test set size as much as possible. We report on several postprocessing methods to reduce the storage requirements of a given test set and present experimental evidence pointing to the possibility of reducing the storage requirements by using appropriate compaction objectives during test generation.