High-Performance Cryptographic SoC Virtual Prototyping Platform Based on RISC-V VP

Abstract

Hardware processors and optimization for secure operations in embedded devices have been a research hotspot in recent years. To full use of the limited computing and storage resources in embedded devices, it is necessary to explore the design space of software and hardware architectures in the early stage of SoC design. Therefore, SystemC-based electronic system-level (ESL) simulators are very useful for fast hardware modeling and verification. In this paper, we propose and design a SystemC-based cryptographic SoC virtual prototyping (Crypto-SoC VP) to speed up function and performance simulation of embedded security devices. We use RISC-V Crypto-Benchmark to analyze the simulation performance of the Crypto-SoC VP. SM4 crypto-accelerator with different hardware and software modes is also integrated in this VP. The experimental results show the efficiency of our design. The simulation speed on our virtual prototyping is over 50 times that of the traditional RTL simulation, while the simulation difference is only about 5%.