{"title":"Error detection of arithmetic circuits using a residue checker with signed-digit number system","authors":"Shugang Wei, K. Shimizu","doi":"10.1109/DFTVS.2001.966754","DOIUrl":null,"url":null,"abstract":"An error detection method for arithmetic circuits is proposed, by using a residue checker which consists of a number of residue arithmetic circuits designed based on radix-2 signed-digit (SD) number arithmetic. Fast modulo m(m=2/sup p//spl plusmn/1) multipliers and binary-to-residue number converters are constructed with a binary tree structure of modulo m SD adders. The modulo m addition is implemented by using a p-digit SD adder, so that the modulo m addition time is independent of the word length of operands. Therefore, the modulo m multiplication is performed in a time proportional to log/sub 2/p and an n-bit binary number is converted into a p-digit SD residue number in a time proportional to log/sub 2/(n/p). The presented residue arithmetic circuits can be applied to error detection for a large product-sum circuit.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"200 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFTVS.2001.966754","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
An error detection method for arithmetic circuits is proposed, by using a residue checker which consists of a number of residue arithmetic circuits designed based on radix-2 signed-digit (SD) number arithmetic. Fast modulo m(m=2/sup p//spl plusmn/1) multipliers and binary-to-residue number converters are constructed with a binary tree structure of modulo m SD adders. The modulo m addition is implemented by using a p-digit SD adder, so that the modulo m addition time is independent of the word length of operands. Therefore, the modulo m multiplication is performed in a time proportional to log/sub 2/p and an n-bit binary number is converted into a p-digit SD residue number in a time proportional to log/sub 2/(n/p). The presented residue arithmetic circuits can be applied to error detection for a large product-sum circuit.
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