Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966748
Y. Audet, G. Chapman
Digital cameras are growing ever larger in silicon area and pixel count, which increases the occurrence of defects at fabrication time, or dead pixels that develop over their lifetime. An active pixel sensor self-correcting for most common faults is created by splitting the photodiode and readout transistors into two parallel portions with only a small area cost. Simulations show operation is the same for a single large device with no faults. When one half of the redundant pixel is stuck at low, output over a wide current range is reduced by 1.98 to 2.01. For one half stuck at high, faults output, after offset removal, is reduced by a factor of 1.85 to 1.92. Hence self-correction of the pixel can be performed with good accuracy via a simple shift circuit and with high accuracy with digital processing. Variation in transistor threshold voltages between the pixel halves of even 10% only causes modification of factors by 2-4%, hence giving a small effect.
{"title":"Design of a self-correcting active pixel sensor","authors":"Y. Audet, G. Chapman","doi":"10.1109/DFTVS.2001.966748","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966748","url":null,"abstract":"Digital cameras are growing ever larger in silicon area and pixel count, which increases the occurrence of defects at fabrication time, or dead pixels that develop over their lifetime. An active pixel sensor self-correcting for most common faults is created by splitting the photodiode and readout transistors into two parallel portions with only a small area cost. Simulations show operation is the same for a single large device with no faults. When one half of the redundant pixel is stuck at low, output over a wide current range is reduced by 1.98 to 2.01. For one half stuck at high, faults output, after offset removal, is reduced by a factor of 1.85 to 1.92. Hence self-correction of the pixel can be performed with good accuracy via a simple shift circuit and with high accuracy with digital processing. Variation in transistor threshold voltages between the pixel halves of even 10% only causes modification of factors by 2-4%, hence giving a small effect.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128683226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966788
Mandeep Singh, I. Koren
The reliability of systems used in space, avionic and biomedical applications is highly critical. Such systems consist of an analog front-end to collect data, an ADC to convert the collected data to digital form and a digital unit to process it. The reliability of these systems is affected by the ability of its constituent blocks to tolerate faults. Therefore, it is necessary to increase the reliability of ADCs to ensure a highly reliable critical system. This paper illustrates the steps involved in the reliability enhancement of ADCs by first proposing a methodology for fault sensitivity analysis and then illustrating redesign techniques to improve the reliability of the highly sensitive(to faults) blocks.
{"title":"Reliability enhancement of analog-to-digital converters (ADCs)","authors":"Mandeep Singh, I. Koren","doi":"10.1109/DFTVS.2001.966788","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966788","url":null,"abstract":"The reliability of systems used in space, avionic and biomedical applications is highly critical. Such systems consist of an analog front-end to collect data, an ADC to convert the collected data to digital form and a digital unit to process it. The reliability of these systems is affected by the ability of its constituent blocks to tolerate faults. Therefore, it is necessary to increase the reliability of ADCs to ensure a highly reliable critical system. This paper illustrates the steps involved in the reliability enhancement of ADCs by first proposing a methodology for fault sensitivity analysis and then illustrating redesign techniques to improve the reliability of the highly sensitive(to faults) blocks.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134380388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966782
K. Namba, E. Fujiwara
This paper presents the code which corrects single bit errors in any location of the word as well as 1-bit burst errors occurred in an important part of the word. The proposed code is designed by product of the parity check matrix of the 1-bit burst error correcting codes and the matrix which converts input unequal errors into equal errors. This paper also demonstrates the evaluation of the code, and presents the extended codes with two-level burst error correcting capabilities by interleaving.
{"title":"Unequal error protection codes with two-level burst and capabilities","authors":"K. Namba, E. Fujiwara","doi":"10.1109/DFTVS.2001.966782","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966782","url":null,"abstract":"This paper presents the code which corrects single bit errors in any location of the word as well as 1-bit burst errors occurred in an important part of the word. The proposed code is designed by product of the parity check matrix of the 1-bit burst error correcting codes and the matrix which converts input unequal errors into equal errors. This paper also demonstrates the evaluation of the code, and presents the extended codes with two-level burst error correcting capabilities by interleaving.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115119623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966775
J. Gracia, J. Baraza, D. Gil, P. Gil
Compares different VHDL-based fault injection techniques: simulator commands, saboteurs and mutants for the validation of fault tolerant systems. Some extensions and implementation designs of these techniques have been introduced. Also, a wide set of non-usual fault models have been implemented. As an application, a fault tolerant microcomputer system has been validated. Faults have been injected using an injection tool developed by the GSTF. We have injected both transient and permanent faults on the system model, using two different workloads. We have studied the pathology of the propagated errors, measured their latencies, and calculated both detection and recovery coverages. Preliminary results show that coverages for transient faults can be obtained quite accurately with any of the three techniques. This enables the use of different abstraction level models for the same system. We have also verified significant differences in implementation and simulation cost between the studied injection techniques.
{"title":"Comparison and application of different VHDL-based fault injection techniques","authors":"J. Gracia, J. Baraza, D. Gil, P. Gil","doi":"10.1109/DFTVS.2001.966775","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966775","url":null,"abstract":"Compares different VHDL-based fault injection techniques: simulator commands, saboteurs and mutants for the validation of fault tolerant systems. Some extensions and implementation designs of these techniques have been introduced. Also, a wide set of non-usual fault models have been implemented. As an application, a fault tolerant microcomputer system has been validated. Faults have been injected using an injection tool developed by the GSTF. We have injected both transient and permanent faults on the system model, using two different workloads. We have studied the pathology of the propagated errors, measured their latencies, and calculated both detection and recovery coverages. Preliminary results show that coverages for transient faults can be obtained quite accurately with any of the three techniques. This enables the use of different abstraction level models for the same system. We have also verified significant differences in implementation and simulation cost between the studied injection techniques.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"168 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116315950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966760
Xiaowei Li, Huawei Li, Y. Min
Presents an approach to reducing power dissipation during at-speed test application. Based on re-ordering of the test-pair sequences, the switching activities of the circuit-under-test during test application can be minimized. Hamming distance between test-pairs is defined to guide test-pair re-ordering. It minimizes power dissipation during test application without reducing delay fault coverage. Experimental results are presented to demonstrate a reduction of power dissipation during test application in the range from 84.69 to 98.08%.
{"title":"Reducing power dissipation during at-speed test application","authors":"Xiaowei Li, Huawei Li, Y. Min","doi":"10.1109/DFTVS.2001.966760","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966760","url":null,"abstract":"Presents an approach to reducing power dissipation during at-speed test application. Based on re-ordering of the test-pair sequences, the switching activities of the circuit-under-test during test application can be minimized. Hamming distance between test-pairs is defined to guide test-pair re-ordering. It minimizes power dissipation during test application without reducing delay fault coverage. Experimental results are presented to demonstrate a reduction of power dissipation during test application in the range from 84.69 to 98.08%.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123922059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966756
R. Leveugle, R. Cercueil
With the increasing probability of transient faults such as bit-flips due to SEUs and the increasing complexity of integrated circuits, the need for integrated mechanisms providing online error detection or fault tolerance is becoming a major concern, not only for classically critical applications, but also for circuits used in everyday life. This paper reports on a tool automating the implementation of some mechanisms by inserting modifications in high-level VHDL descriptions. The modifications are compatible with industrial design flows based on commercial synthesis and simulation tools. Implementation results are presented and compared with results previously obtained using a specific synthesis tool.
{"title":"High level modifications of VHDL descriptions for on-line test or fault tolerance","authors":"R. Leveugle, R. Cercueil","doi":"10.1109/DFTVS.2001.966756","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966756","url":null,"abstract":"With the increasing probability of transient faults such as bit-flips due to SEUs and the increasing complexity of integrated circuits, the need for integrated mechanisms providing online error detection or fault tolerance is becoming a major concern, not only for classically critical applications, but also for circuits used in everyday life. This paper reports on a tool automating the implementation of some mechanisms by inserting modifications in high-level VHDL descriptions. The modifications are compatible with industrial design flows based on commercial synthesis and simulation tools. Implementation results are presented and compared with results previously obtained using a specific synthesis tool.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129668314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966755
T. Ngai, E. Swartzlander, Chen He
Presents an enhanced concurrent error correcting arithmetic unit design methodology using alternating logic, which is motivated by the time shared triple modular redundancy (TMR) technique. With help from alternating logic, this new design approach will result in a higher reliability, i.e., 100% stuck-at faults can be detected, modest hardware delay and overhead. The basic idea is to add inverters and multiplexers in front of and behind the arithmetic unit and to let some control logic choose the path for the data. This design methodology can be applied to any system with hardware redundancy. For demonstration and comparison, 16-bit VLSI ripple carry adders are designed and verified using both the time shared TMR technique and the time shared TMR with alternating logic strategy. It is shown from the simulation results that the proposed approach has higher reliability with only a small increase in hardware delay.
{"title":"Enhanced concurrent error correcting arithmetic unit design using alternating logic","authors":"T. Ngai, E. Swartzlander, Chen He","doi":"10.1109/DFTVS.2001.966755","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966755","url":null,"abstract":"Presents an enhanced concurrent error correcting arithmetic unit design methodology using alternating logic, which is motivated by the time shared triple modular redundancy (TMR) technique. With help from alternating logic, this new design approach will result in a higher reliability, i.e., 100% stuck-at faults can be detected, modest hardware delay and overhead. The basic idea is to add inverters and multiplexers in front of and behind the arithmetic unit and to let some control logic choose the path for the data. This design methodology can be applied to any system with hardware redundancy. For demonstration and comparison, 16-bit VLSI ripple carry adders are designed and verified using both the time shared TMR technique and the time shared TMR with alternating logic strategy. It is shown from the simulation results that the proposed approach has higher reliability with only a small increase in hardware delay.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"445 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122806803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966799
S. Pontarelli, G. Cardarilli, A. Malvoni, M. Ottavi, M. Re, A. Salsano
This paper presents a design methodology for fault tolerant sequential systems implemented on System on Chip (SoC). In the paper, as an example, a complex fault tolerant finite state machine has been mapped on the FPGA contained in the SoC. The fault identification has been obtained by using a checker permitting the identification of classes of faults. When a fault is detected, an interrupt for the microcontroller is generated and the interrupt handling routine partially reprograms the FPGA to override the part of memory configuring the faulty block. The architectures of the SoCs recently appeared on the market are characterized by a very efficient interaction between the microcontroller and the FPGA allowing a very efficient implementation of the fault detection and fault recovery strategy. A test bed of the proposed methodology has been implemented on the recently presented Atmel AT94K FPSLIC (Field Programmable System Level Integrated Circuits).
{"title":"System-on-chip oriented fault-tolerant sequential systems implementation methodology","authors":"S. Pontarelli, G. Cardarilli, A. Malvoni, M. Ottavi, M. Re, A. Salsano","doi":"10.1109/DFTVS.2001.966799","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966799","url":null,"abstract":"This paper presents a design methodology for fault tolerant sequential systems implemented on System on Chip (SoC). In the paper, as an example, a complex fault tolerant finite state machine has been mapped on the FPGA contained in the SoC. The fault identification has been obtained by using a checker permitting the identification of classes of faults. When a fault is detected, an interrupt for the microcontroller is generated and the interrupt handling routine partially reprograms the FPGA to override the part of memory configuring the faulty block. The architectures of the SoCs recently appeared on the market are characterized by a very efficient interaction between the microcontroller and the FPGA allowing a very efficient implementation of the fault detection and fault recovery strategy. A test bed of the proposed methodology has been implemented on the recently presented Atmel AT94K FPSLIC (Field Programmable System Level Integrated Circuits).","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"160 30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122847120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966772
Wei-Je Huang, S. Mitra, E. McCluskey
Run-time fault location in field-programmable gate arrays (FPGAs) is important because the resulting diagnostic information can be used to reconfigure the FPGA to tolerate permanent faults. In order to minimize system downtime and increase availability, a fault location technique with very short diagnostic latency is desired. We present a fast technique for run-time FPGA fault location that can be used for high-availability reconfigurable systems. By integrating FPGA fault tolerance and concurrent error detection (CED) techniques, our approach can achieve significant availability improvement by minimizing the number of reconfigurations required for FPGA fault location and recovery. The area overhead of our approach is studied and illustrated using applications implemented in FPGAs.
{"title":"Fast run-time fault location in dependable FPGA-based applications","authors":"Wei-Je Huang, S. Mitra, E. McCluskey","doi":"10.1109/DFTVS.2001.966772","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966772","url":null,"abstract":"Run-time fault location in field-programmable gate arrays (FPGAs) is important because the resulting diagnostic information can be used to reconfigure the FPGA to tolerate permanent faults. In order to minimize system downtime and increase availability, a fault location technique with very short diagnostic latency is desired. We present a fast technique for run-time FPGA fault location that can be used for high-availability reconfigurable systems. By integrating FPGA fault tolerance and concurrent error detection (CED) techniques, our approach can achieve significant availability improvement by minimizing the number of reconfigurations required for FPGA fault location and recovery. The area overhead of our approach is studied and illustrated using applications implemented in FPGAs.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"580 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123130645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966793
A. Matrosova, S. Ostanin, I. Levin
This paper presents a method for designing totally self-checking synchronous sequential circuits (SSC), and investigates their behavior in presence of transient faults. We deal with the case when the circuit is able to recover after the number of clocks. We call SSC owing this property as a survivable SSC. A concept of a partially monotonous SSC is developed in the paper. It is proven that the partially monotonous SSCs are survivable.
{"title":"Survivable self-checking sequential circuits","authors":"A. Matrosova, S. Ostanin, I. Levin","doi":"10.1109/DFTVS.2001.966793","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966793","url":null,"abstract":"This paper presents a method for designing totally self-checking synchronous sequential circuits (SSC), and investigates their behavior in presence of transient faults. We deal with the case when the circuit is able to recover after the number of clocks. We call SSC owing this property as a survivable SSC. A concept of a partially monotonous SSC is developed in the paper. It is proven that the partially monotonous SSCs are survivable.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126244691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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