Formal Verification of Abstract System and Protocol Specifications

Axel Schneider, T. Bluhm, Tobias Renner, U. Heinkel, Joachim Knäblein, Reynaldo Zavala
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引用次数: 9

Abstract

Formal methods such as automated model checking are used commercially for digital circuit design verification. These techniques find errors early in the product cycle, which improves development time and cost. By contrast, the current practice in complex system design is to specify system functions and protocol details in natural language. Some errors are found early by manual inspections, but others are only revealed during implementation testing or by costly field failures. We describe our application of formal specification and model checking to real telecom product development, and enumerate the classes of specification errors that these formal techniques revealed at an early stage of the development cycle
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抽象系统和协议规范的形式化验证
正式的方法,如自动模型检查被商业上用于数字电路设计验证。这些技术可以在产品周期的早期发现错误,从而改善开发时间和成本。相比之下,目前复杂系统设计的做法是用自然语言来指定系统功能和协议细节。有些错误可以通过人工检查早期发现,但其他错误仅在实现测试期间或昂贵的现场故障中发现。我们描述了形式化规范和模型检查在实际电信产品开发中的应用,并列举了这些形式化技术在开发周期的早期阶段所揭示的规范错误的类别
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