Impact of System-in-Package in side-by-side discrete SoC-DRAM configurations on SI, PI and thermal performance

Abstract

In this paper, a SoC (System on Chip) - DRAM configured 2D planar side-by-side SiP (System in Package) is compared to a conventional SCP (single chip package) on board with respect to SI (signal integrity), PI (power integrity), and thermal performance. In SI and PI aspects, eye aperture widths of DQ signals are used as a figure of merit for performance decisions. SiP's shorter channel lengths and fewer discontinuities can result in wider eye apertures but its longer and smaller PDN (power delivery network) shapes narrows them. In order to enhance SiP PI and consequent wider eye aperture width, De-cap (decoupling capacitor) values are swept and their numbers, capacities and locations are changed. Finally, the optimal De-cap placement to achieve robust PI performance can be found. However, since SiP has shorter distance and larger thermal coupling between SoC and DRAM, SiP configuration shows a comparatively worse thermal performance than SCP on board. The thermal comparison is based on two temperatures taken from the top surfaces of the SoC and DRAM, and the leakage power of the two SoC's. Through this comparison study between SCP on board and SiP, a basic understanding on how to adopt advanced DDR features in SiP application for D-TV (digital TV) can be obtained.